/* SPDX-License-Identifier: Apache-2.0 */

#ifndef __SUN55IW3_REG_CCU_H__
#define __SUN55IW3_REG_CCU_H__

#include <reg-ncat.h>

#define PLL_CPU0_CTRL_REG 0x00000000//PLL_CPU0 Control Register
#define PLL_CPU0_CTRL_REG_PLL_EN_OFFSET 31
#define PLL_CPU0_CTRL_REG_PLL_EN_CLEAR_MASK 0x80000000
#define PLL_CPU0_CTRL_REG_PLL_EN_DISABLE 0x0
#define PLL_CPU0_CTRL_REG_PLL_EN_ENABLE 0x1
#define PLL_CPU0_CTRL_REG_PLL_LDO_EN_OFFSET 30
#define PLL_CPU0_CTRL_REG_PLL_LDO_EN_CLEAR_MASK 0x40000000
#define PLL_CPU0_CTRL_REG_PLL_LDO_EN_DISABLE 0x0
#define PLL_CPU0_CTRL_REG_PLL_LDO_EN_ENABLE 0x1
#define PLL_CPU0_CTRL_REG_LOCK_ENABLE_OFFSET 29
#define PLL_CPU0_CTRL_REG_LOCK_ENABLE_CLEAR_MASK 0x20000000
#define PLL_CPU0_CTRL_REG_LOCK_ENABLE_DISABLE 0x0
#define PLL_CPU0_CTRL_REG_LOCK_ENABLE_ENABLE 0x1
#define PLL_CPU0_CTRL_REG_LOCK_OFFSET 28
#define PLL_CPU0_CTRL_REG_LOCK_CLEAR_MASK 0x10000000
#define PLL_CPU0_CTRL_REG_LOCK_UNLOCKED 0x0
#define PLL_CPU0_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0x1
#define PLL_CPU0_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27
#define PLL_CPU0_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK 0x08000000
#define PLL_CPU0_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0x0
#define PLL_CPU0_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0x1
#define PLL_CPU0_CTRL_REG_PLL_LOCK_TIME_OFFSET 24
#define PLL_CPU0_CTRL_REG_PLL_LOCK_TIME_CLEAR_MASK 0x07000000
#define PLL_CPU0_CTRL_REG_PLL_N_OFFSET 8
#define PLL_CPU0_CTRL_REG_PLL_N_CLEAR_MASK 0x0000ff00
#define PLL_CPU0_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6
#define PLL_CPU0_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK 0x000000c0
#define PLL_CPU0_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0x00
#define PLL_CPU0_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0x01
#define PLL_CPU0_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0x10
#define PLL_CPU0_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5
#define PLL_CPU0_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK 0x00000020
#define PLL_CPU0_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0x0
#define PLL_CPU0_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0x1
#define PLL_CPU0_CTRL_REG_PLL_M_OFFSET 0
#define PLL_CPU0_CTRL_REG_PLL_M_CLEAR_MASK 0x00000003

#define PLL_CPU1_CTRL_REG 0x00000004//PLL_CPU1 Control Register
#define PLL_CPU1_CTRL_REG_PLL_EN_OFFSET 31
#define PLL_CPU1_CTRL_REG_PLL_EN_CLEAR_MASK 0x80000000
#define PLL_CPU1_CTRL_REG_PLL_EN_DISABLE 0x0
#define PLL_CPU1_CTRL_REG_PLL_EN_ENABLE 0x1
#define PLL_CPU1_CTRL_REG_PLL_LDO_EN_OFFSET 30
#define PLL_CPU1_CTRL_REG_PLL_LDO_EN_CLEAR_MASK 0x40000000
#define PLL_CPU1_CTRL_REG_PLL_LDO_EN_DISABLE 0x0
#define PLL_CPU1_CTRL_REG_PLL_LDO_EN_ENABLE 0x1
#define PLL_CPU1_CTRL_REG_LOCK_ENABLE_OFFSET 29
#define PLL_CPU1_CTRL_REG_LOCK_ENABLE_CLEAR_MASK 0x20000000
#define PLL_CPU1_CTRL_REG_LOCK_ENABLE_DISABLE 0x0
#define PLL_CPU1_CTRL_REG_LOCK_ENABLE_ENABLE 0x1
#define PLL_CPU1_CTRL_REG_LOCK_OFFSET 28
#define PLL_CPU1_CTRL_REG_LOCK_CLEAR_MASK 0x10000000
#define PLL_CPU1_CTRL_REG_LOCK_UNLOCKED 0x0
#define PLL_CPU1_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0x1
#define PLL_CPU1_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27
#define PLL_CPU1_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK 0x08000000
#define PLL_CPU1_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0x0
#define PLL_CPU1_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0x1
#define PLL_CPU1_CTRL_REG_PLL_LOCK_TIME_OFFSET 24
#define PLL_CPU1_CTRL_REG_PLL_LOCK_TIME_CLEAR_MASK 0x07000000
#define PLL_CPU1_CTRL_REG_PLL_N_OFFSET 8
#define PLL_CPU1_CTRL_REG_PLL_N_CLEAR_MASK 0x0000ff00
#define PLL_CPU1_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6
#define PLL_CPU1_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK 0x000000c0
#define PLL_CPU1_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0x00
#define PLL_CPU1_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0x01
#define PLL_CPU1_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0x10
#define PLL_CPU1_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5
#define PLL_CPU1_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK 0x00000020
#define PLL_CPU1_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0x0
#define PLL_CPU1_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0x1
#define PLL_CPU1_CTRL_REG_PLL_M_OFFSET 0
#define PLL_CPU1_CTRL_REG_PLL_M_CLEAR_MASK 0x00000003

#define PLL_CPU2_CTRL_REG 0x00000008//PLL_CPU2 Control Register
#define PLL_CPU2_CTRL_REG_PLL_EN_OFFSET 31
#define PLL_CPU2_CTRL_REG_PLL_EN_CLEAR_MASK 0x80000000
#define PLL_CPU2_CTRL_REG_PLL_EN_DISABLE 0x0
#define PLL_CPU2_CTRL_REG_PLL_EN_ENABLE 0x1
#define PLL_CPU2_CTRL_REG_PLL_LDO_EN_OFFSET 30
#define PLL_CPU2_CTRL_REG_PLL_LDO_EN_CLEAR_MASK 0x40000000
#define PLL_CPU2_CTRL_REG_PLL_LDO_EN_DISABLE 0x0
#define PLL_CPU2_CTRL_REG_PLL_LDO_EN_ENABLE 0x1
#define PLL_CPU2_CTRL_REG_LOCK_ENABLE_OFFSET 29
#define PLL_CPU2_CTRL_REG_LOCK_ENABLE_CLEAR_MASK 0x20000000
#define PLL_CPU2_CTRL_REG_LOCK_ENABLE_DISABLE 0x0
#define PLL_CPU2_CTRL_REG_LOCK_ENABLE_ENABLE 0x1
#define PLL_CPU2_CTRL_REG_LOCK_OFFSET 28
#define PLL_CPU2_CTRL_REG_LOCK_CLEAR_MASK 0x10000000
#define PLL_CPU2_CTRL_REG_LOCK_UNLOCKED 0x0
#define PLL_CPU2_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0x1
#define PLL_CPU2_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27
#define PLL_CPU2_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK 0x08000000
#define PLL_CPU2_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0x0
#define PLL_CPU2_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0x1
#define PLL_CPU2_CTRL_REG_PLL_LOCK_TIME_OFFSET 24
#define PLL_CPU2_CTRL_REG_PLL_LOCK_TIME_CLEAR_MASK 0x07000000
#define PLL_CPU2_CTRL_REG_PLL_N_OFFSET 8
#define PLL_CPU2_CTRL_REG_PLL_N_CLEAR_MASK 0x0000ff00
#define PLL_CPU2_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6
#define PLL_CPU2_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK 0x000000c0
#define PLL_CPU2_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0x00
#define PLL_CPU2_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0x01
#define PLL_CPU2_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0x10
#define PLL_CPU2_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5
#define PLL_CPU2_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK 0x00000020
#define PLL_CPU2_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0x0
#define PLL_CPU2_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0x1
#define PLL_CPU2_CTRL_REG_PLL_M_OFFSET 0
#define PLL_CPU2_CTRL_REG_PLL_M_CLEAR_MASK 0x00000003

#define PLL_CPU3_CTRL_REG 0x00000008//PLL_CPU2 Control Register
#define PLL_CPU3_CTRL_REG_PLL_EN_OFFSET 31
#define PLL_CPU3_CTRL_REG_PLL_EN_CLEAR_MASK 0x80000000
#define PLL_CPU3_CTRL_REG_PLL_EN_DISABLE 0x0
#define PLL_CPU3_CTRL_REG_PLL_EN_ENABLE 0x1
#define PLL_CPU3_CTRL_REG_PLL_LDO_EN_OFFSET 30
#define PLL_CPU3_CTRL_REG_PLL_LDO_EN_CLEAR_MASK 0x40000000
#define PLL_CPU3_CTRL_REG_PLL_LDO_EN_DISABLE 0x0
#define PLL_CPU3_CTRL_REG_PLL_LDO_EN_ENABLE 0x1
#define PLL_CPU3_CTRL_REG_LOCK_ENABLE_OFFSET 29
#define PLL_CPU3_CTRL_REG_LOCK_ENABLE_CLEAR_MASK 0x20000000
#define PLL_CPU3_CTRL_REG_LOCK_ENABLE_DISABLE 0x0
#define PLL_CPU3_CTRL_REG_LOCK_ENABLE_ENABLE 0x1
#define PLL_CPU3_CTRL_REG_LOCK_OFFSET 28
#define PLL_CPU3_CTRL_REG_LOCK_CLEAR_MASK 0x10000000
#define PLL_CPU3_CTRL_REG_LOCK_UNLOCKED 0x0
#define PLL_CPU3_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0x1
#define PLL_CPU3_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27
#define PLL_CPU3_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK 0x08000000
#define PLL_CPU3_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0x0
#define PLL_CPU3_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0x1
#define PLL_CPU3_CTRL_REG_PLL_LOCK_TIME_OFFSET 24
#define PLL_CPU3_CTRL_REG_PLL_LOCK_TIME_CLEAR_MASK 0x07000000
#define PLL_CPU3_CTRL_REG_PLL_N_OFFSET 8
#define PLL_CPU3_CTRL_REG_PLL_N_CLEAR_MASK 0x0000ff00
#define PLL_CPU3_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6
#define PLL_CPU3_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK 0x000000c0
#define PLL_CPU3_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0x00
#define PLL_CPU3_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0x01
#define PLL_CPU3_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0x10
#define PLL_CPU3_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5
#define PLL_CPU3_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK 0x00000020
#define PLL_CPU3_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0x0
#define PLL_CPU3_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0x1
#define PLL_CPU3_CTRL_REG_PLL_M_OFFSET 0

#define PLL_DDR_CTRL_REG 0x00000010//PLL_DDR Control Register
#define PLL_DDR_CTRL_REG_PLL_EN_OFFSET 31
#define PLL_DDR_CTRL_REG_PLL_EN_CLEAR_MASK 0x80000000
#define PLL_DDR_CTRL_REG_PLL_EN_DISABLE 0x0
#define PLL_DDR_CTRL_REG_PLL_EN_ENABLE 0x1
#define PLL_DDR_CTRL_REG_PLL_LDO_EN_OFFSET 30
#define PLL_DDR_CTRL_REG_PLL_LDO_EN_CLEAR_MASK 0x40000000
#define PLL_DDR_CTRL_REG_PLL_LDO_EN_DISABLE 0x0
#define PLL_DDR_CTRL_REG_PLL_LDO_EN_ENABLE 0x1
#define PLL_DDR_CTRL_REG_LOCK_ENABLE_OFFSET 29
#define PLL_DDR_CTRL_REG_LOCK_ENABLE_CLEAR_MASK 0x20000000
#define PLL_DDR_CTRL_REG_LOCK_ENABLE_DISABLE 0x0
#define PLL_DDR_CTRL_REG_LOCK_ENABLE_ENABLE 0x1
#define PLL_DDR_CTRL_REG_LOCK_OFFSET 28
#define PLL_DDR_CTRL_REG_LOCK_CLEAR_MASK 0x10000000
#define PLL_DDR_CTRL_REG_LOCK_UNLOCKED 0x0
#define PLL_DDR_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0x1
#define PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27
#define PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK 0x08000000
#define PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0x0
#define PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0x1
#define PLL_DDR_CTRL_REG_PLL_SDM_EN_OFFSET 24
#define PLL_DDR_CTRL_REG_PLL_SDM_EN_CLEAR_MASK 0x01000000
#define PLL_DDR_CTRL_REG_PLL_SDM_EN_DISABLE 0x0
#define PLL_DDR_CTRL_REG_PLL_SDM_EN_ENABLE 0x1
#define PLL_DDR_CTRL_REG_PLL_N_OFFSET 8
#define PLL_DDR_CTRL_REG_PLL_N_CLEAR_MASK 0x0000ff00
#define PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6
#define PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK 0x000000c0
#define PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0x00
#define PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0x01
#define PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0x10
#define PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5
#define PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK 0x00000020
#define PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0x0
#define PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0x1
#define PLL_DDR_CTRL_REG_PLL_INPUT_DIV2_OFFSET 1
#define PLL_DDR_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK 0x00000002
#define PLL_DDR_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET 0
#define PLL_DDR_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK 0x00000001

#define PLL_PERI0_CTRL_REG 0x00000020//PLL_PERI0 Control Register
#define PLL_PERI0_CTRL_REG_PLL_EN_OFFSET 31
#define PLL_PERI0_CTRL_REG_PLL_EN_CLEAR_MASK 0x80000000
#define PLL_PERI0_CTRL_REG_PLL_EN_DISABLE 0x0
#define PLL_PERI0_CTRL_REG_PLL_EN_ENABLE 0x1
#define PLL_PERI0_CTRL_REG_PLL_LDO_EN_OFFSET 30
#define PLL_PERI0_CTRL_REG_PLL_LDO_EN_CLEAR_MASK 0x40000000
#define PLL_PERI0_CTRL_REG_PLL_LDO_EN_DISABLE 0x0
#define PLL_PERI0_CTRL_REG_PLL_LDO_EN_ENABLE 0x1
#define PLL_PERI0_CTRL_REG_LOCK_ENABLE_OFFSET 29
#define PLL_PERI0_CTRL_REG_LOCK_ENABLE_CLEAR_MASK 0x20000000
#define PLL_PERI0_CTRL_REG_LOCK_ENABLE_DISABLE 0x0
#define PLL_PERI0_CTRL_REG_LOCK_ENABLE_ENABLE 0x1
#define PLL_PERI0_CTRL_REG_LOCK_OFFSET 28
#define PLL_PERI0_CTRL_REG_LOCK_CLEAR_MASK 0x10000000
#define PLL_PERI0_CTRL_REG_LOCK_UNLOCKED 0x0
#define PLL_PERI0_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0x1
#define PLL_PERI0_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27
#define PLL_PERI0_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK 0x08000000
#define PLL_PERI0_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0x0
#define PLL_PERI0_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0x1
#define PLL_PERI0_CTRL_REG_PLL_SDM_EN_OFFSET 24
#define PLL_PERI0_CTRL_REG_PLL_SDM_EN_CLEAR_MASK 0x01000000
#define PLL_PERI0_CTRL_REG_PLL_SDM_EN_DISABLE 0x0
#define PLL_PERI0_CTRL_REG_PLL_SDM_EN_ENABLE 0x1
#define PLL_PERI0_CTRL_REG_PLL_P1_OFFSET 20
#define PLL_PERI0_CTRL_REG_PLL_P1_CLEAR_MASK 0x00700000
#define PLL_PERI0_CTRL_REG_PLL_P0_OFFSET 16
#define PLL_PERI0_CTRL_REG_PLL_P0_CLEAR_MASK 0x00070000
#define PLL_PERI0_CTRL_REG_PLL_N_OFFSET 8
#define PLL_PERI0_CTRL_REG_PLL_N_CLEAR_MASK 0x0000ff00
#define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6
#define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK 0x000000c0
#define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0x00
#define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0x01
#define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0x10
#define PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5
#define PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK 0x00000020
#define PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0x0
#define PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0x1
#define PLL_PERI0_CTRL_REG_PLL_P2_OFFSET 2
#define PLL_PERI0_CTRL_REG_PLL_P2_CLEAR_MASK 0x0000001c
#define PLL_PERI0_CTRL_REG_PLL_INPUT_DIV2_OFFSET 1
#define PLL_PERI0_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK 0x00000002

#define PLL_PERI1_CTRL_REG 0x00000028//PLL_PERI1 Control Register
#define PLL_PERI1_CTRL_REG_PLL_EN_OFFSET 31
#define PLL_PERI1_CTRL_REG_PLL_EN_CLEAR_MASK 0x80000000
#define PLL_PERI1_CTRL_REG_PLL_EN_DISABLE 0x0
#define PLL_PERI1_CTRL_REG_PLL_EN_ENABLE 0x1
#define PLL_PERI1_CTRL_REG_PLL_LDO_EN_OFFSET 30
#define PLL_PERI1_CTRL_REG_PLL_LDO_EN_CLEAR_MASK 0x40000000
#define PLL_PERI1_CTRL_REG_PLL_LDO_EN_DISABLE 0x0
#define PLL_PERI1_CTRL_REG_PLL_LDO_EN_ENABLE 0x1
#define PLL_PERI1_CTRL_REG_LOCK_ENABLE_OFFSET 29
#define PLL_PERI1_CTRL_REG_LOCK_ENABLE_CLEAR_MASK 0x20000000
#define PLL_PERI1_CTRL_REG_LOCK_ENABLE_DISABLE 0x0
#define PLL_PERI1_CTRL_REG_LOCK_ENABLE_ENABLE 0x1
#define PLL_PERI1_CTRL_REG_LOCK_OFFSET 28
#define PLL_PERI1_CTRL_REG_LOCK_CLEAR_MASK 0x10000000
#define PLL_PERI1_CTRL_REG_LOCK_UNLOCKED 0x0
#define PLL_PERI1_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0x1
#define PLL_PERI1_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27
#define PLL_PERI1_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK 0x08000000
#define PLL_PERI1_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0x0
#define PLL_PERI1_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0x1
#define PLL_PERI1_CTRL_REG_PLL_SDM_EN_OFFSET 24
#define PLL_PERI1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK 0x01000000
#define PLL_PERI1_CTRL_REG_PLL_SDM_EN_DISABLE 0x0
#define PLL_PERI1_CTRL_REG_PLL_SDM_EN_ENABLE 0x1
#define PLL_PERI1_CTRL_REG_PLL_P1_OFFSET 20
#define PLL_PERI1_CTRL_REG_PLL_P1_CLEAR_MASK 0x00700000
#define PLL_PERI1_CTRL_REG_PLL_P0_OFFSET 16
#define PLL_PERI1_CTRL_REG_PLL_P0_CLEAR_MASK 0x00070000
#define PLL_PERI1_CTRL_REG_PLL_N_OFFSET 8
#define PLL_PERI1_CTRL_REG_PLL_N_CLEAR_MASK 0x0000ff00
#define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6
#define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK 0x000000c0
#define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0x00
#define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0x01
#define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0x10
#define PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5
#define PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK 0x00000020
#define PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0x0
#define PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0x1
#define PLL_PERI1_CTRL_REG_PLL_P2_OFFSET 2
#define PLL_PERI1_CTRL_REG_PLL_P2_CLEAR_MASK 0x0000001c
#define PLL_PERI1_CTRL_REG_PLL_INPUT_DIV2_OFFSET 1
#define PLL_PERI1_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK 0x00000002

#define PLL_GPU_CTRL_REG 0x00000030//PLL_GPU Control Register
#define PLL_GPU_CTRL_REG_PLL_EN_OFFSET 31
#define PLL_GPU_CTRL_REG_PLL_EN_CLEAR_MASK 0x80000000
#define PLL_GPU_CTRL_REG_PLL_EN_DISABLE 0x0
#define PLL_GPU_CTRL_REG_PLL_EN_ENABLE 0x1
#define PLL_GPU_CTRL_REG_PLL_LDO_EN_OFFSET 30
#define PLL_GPU_CTRL_REG_PLL_LDO_EN_CLEAR_MASK 0x40000000
#define PLL_GPU_CTRL_REG_PLL_LDO_EN_DISABLE 0x0
#define PLL_GPU_CTRL_REG_PLL_LDO_EN_ENABLE 0x1
#define PLL_GPU_CTRL_REG_LOCK_ENABLE_OFFSET 29
#define PLL_GPU_CTRL_REG_LOCK_ENABLE_CLEAR_MASK 0x20000000
#define PLL_GPU_CTRL_REG_LOCK_ENABLE_DISABLE 0x0
#define PLL_GPU_CTRL_REG_LOCK_ENABLE_ENABLE 0x1
#define PLL_GPU_CTRL_REG_LOCK_OFFSET 28
#define PLL_GPU_CTRL_REG_LOCK_CLEAR_MASK 0x10000000
#define PLL_GPU_CTRL_REG_LOCK_UNLOCKED 0x0
#define PLL_GPU_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0x1
#define PLL_GPU_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27
#define PLL_GPU_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK 0x08000000
#define PLL_GPU_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0x0
#define PLL_GPU_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0x1
#define PLL_GPU_CTRL_REG_PLL_SDM_EN_OFFSET 24
#define PLL_GPU_CTRL_REG_PLL_SDM_EN_CLEAR_MASK 0x01000000
#define PLL_GPU_CTRL_REG_PLL_SDM_EN_DISABLE 0x0
#define PLL_GPU_CTRL_REG_PLL_SDM_EN_ENABLE 0x1
#define PLL_GPU_CTRL_REG_PLL_N_OFFSET 8
#define PLL_GPU_CTRL_REG_PLL_N_CLEAR_MASK 0x0000ff00
#define PLL_GPU_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6
#define PLL_GPU_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK 0x000000c0
#define PLL_GPU_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0x00
#define PLL_GPU_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0x01
#define PLL_GPU_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0x10
#define PLL_GPU_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5
#define PLL_GPU_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK 0x00000020
#define PLL_GPU_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0x0
#define PLL_GPU_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0x1
#define PLL_GPU_CTRL_REG_PLL_INPUT_DIV2_OFFSET 1
#define PLL_GPU_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK 0x00000002
#define PLL_GPU_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET 0
#define PLL_GPU_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK 0x00000001

#define PLL_VIDEO0_CTRL_REG 0x00000040//PLL_VIDEO0 Control Register
#define PLL_VIDEO0_CTRL_REG_PLL_EN_OFFSET 31
#define PLL_VIDEO0_CTRL_REG_PLL_EN_CLEAR_MASK 0x80000000
#define PLL_VIDEO0_CTRL_REG_PLL_EN_DISABLE 0x0
#define PLL_VIDEO0_CTRL_REG_PLL_EN_ENABLE 0x1
#define PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_OFFSET 30
#define PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_CLEAR_MASK 0x40000000
#define PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_DISABLE 0x0
#define PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_ENABLE 0x1
#define PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_OFFSET 29
#define PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_CLEAR_MASK 0x20000000
#define PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_DISABLE 0x0
#define PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_ENABLE 0x1
#define PLL_VIDEO0_CTRL_REG_LOCK_OFFSET 28
#define PLL_VIDEO0_CTRL_REG_LOCK_CLEAR_MASK 0x10000000
#define PLL_VIDEO0_CTRL_REG_LOCK_UNLOCKED 0x0
#define PLL_VIDEO0_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0x1
#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27
#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK 0x08000000
#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0x0
#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0x1
#define PLL_VIDEO0_CTRL_REG_PLL_SDM_EN_OFFSET 24
#define PLL_VIDEO0_CTRL_REG_PLL_SDM_EN_CLEAR_MASK 0x01000000
#define PLL_VIDEO0_CTRL_REG_PLL_SDM_EN_DISABLE 0x0
#define PLL_VIDEO0_CTRL_REG_PLL_SDM_EN_ENABLE 0x1
#define PLL_VIDEO0_CTRL_REG_PLL_N_OFFSET 8
#define PLL_VIDEO0_CTRL_REG_PLL_N_CLEAR_MASK 0x0000ff00
#define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6
#define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK 0x000000c0
#define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0x00
#define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0x01
#define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0x10
#define PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5
#define PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK 0x00000020
#define PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0x0
#define PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0x1
#define PLL_VIDEO0_CTRL_REG_PLL_INPUT_DIV2_OFFSET 1
#define PLL_VIDEO0_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK 0x00000002
#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET 0
#define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK 0x00000001

#define PLL_VIDEO1_CTRL_REG 0x00000048//PLL_VIDEO1 Control Register
#define PLL_VIDEO1_CTRL_REG_PLL_EN_OFFSET 31
#define PLL_VIDEO1_CTRL_REG_PLL_EN_CLEAR_MASK 0x80000000
#define PLL_VIDEO1_CTRL_REG_PLL_EN_DISABLE 0x0
#define PLL_VIDEO1_CTRL_REG_PLL_EN_ENABLE 0x1
#define PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_OFFSET 30
#define PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_CLEAR_MASK 0x40000000
#define PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_DISABLE 0x0
#define PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_ENABLE 0x1
#define PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_OFFSET 29
#define PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_CLEAR_MASK 0x20000000
#define PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_DISABLE 0x0
#define PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_ENABLE 0x1
#define PLL_VIDEO1_CTRL_REG_LOCK_OFFSET 28
#define PLL_VIDEO1_CTRL_REG_LOCK_CLEAR_MASK 0x10000000
#define PLL_VIDEO1_CTRL_REG_LOCK_UNLOCKED 0x0
#define PLL_VIDEO1_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0x1
#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27
#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK 0x08000000
#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0x0
#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0x1
#define PLL_VIDEO1_CTRL_REG_PLL_SDM_EN_OFFSET 24
#define PLL_VIDEO1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK 0x01000000
#define PLL_VIDEO1_CTRL_REG_PLL_SDM_EN_DISABLE 0x0
#define PLL_VIDEO1_CTRL_REG_PLL_SDM_EN_ENABLE 0x1
#define PLL_VIDEO1_CTRL_REG_PLL_N_OFFSET 8
#define PLL_VIDEO1_CTRL_REG_PLL_N_CLEAR_MASK 0x0000ff00
#define PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6
#define PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK 0x000000c0
#define PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0x00
#define PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0x01
#define PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0x10
#define PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5
#define PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK 0x00000020
#define PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0x0
#define PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0x1
#define PLL_VIDEO1_CTRL_REG_PLL_INPUT_DIV2_OFFSET 1
#define PLL_VIDEO1_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK 0x00000002
#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET 0
#define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK 0x00000001

#define PLL_VIDEO2_CTRL_REG 0x00000050//PLL_VIDEO2 Control Register
#define PLL_VIDEO2_CTRL_REG_PLL_EN_OFFSET 31
#define PLL_VIDEO2_CTRL_REG_PLL_EN_CLEAR_MASK 0x80000000
#define PLL_VIDEO2_CTRL_REG_PLL_EN_DISABLE 0x0
#define PLL_VIDEO2_CTRL_REG_PLL_EN_ENABLE 0x1
#define PLL_VIDEO2_CTRL_REG_PLL_LDO_EN_OFFSET 30
#define PLL_VIDEO2_CTRL_REG_PLL_LDO_EN_CLEAR_MASK 0x40000000
#define PLL_VIDEO2_CTRL_REG_PLL_LDO_EN_DISABLE 0x0
#define PLL_VIDEO2_CTRL_REG_PLL_LDO_EN_ENABLE 0x1
#define PLL_VIDEO2_CTRL_REG_LOCK_ENABLE_OFFSET 29
#define PLL_VIDEO2_CTRL_REG_LOCK_ENABLE_CLEAR_MASK 0x20000000
#define PLL_VIDEO2_CTRL_REG_LOCK_ENABLE_DISABLE 0x0
#define PLL_VIDEO2_CTRL_REG_LOCK_ENABLE_ENABLE 0x1
#define PLL_VIDEO2_CTRL_REG_LOCK_OFFSET 28
#define PLL_VIDEO2_CTRL_REG_LOCK_CLEAR_MASK 0x10000000
#define PLL_VIDEO2_CTRL_REG_LOCK_UNLOCKED 0x0
#define PLL_VIDEO2_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0x1
#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27
#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK 0x08000000
#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0x0
#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0x1
#define PLL_VIDEO2_CTRL_REG_PLL_SDM_EN_OFFSET 24
#define PLL_VIDEO2_CTRL_REG_PLL_SDM_EN_CLEAR_MASK 0x01000000
#define PLL_VIDEO2_CTRL_REG_PLL_SDM_EN_DISABLE 0x0
#define PLL_VIDEO2_CTRL_REG_PLL_SDM_EN_ENABLE 0x1
#define PLL_VIDEO2_CTRL_REG_PLL_N_OFFSET 8
#define PLL_VIDEO2_CTRL_REG_PLL_N_CLEAR_MASK 0x0000ff00
#define PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6
#define PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK 0x000000c0
#define PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0x00
#define PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0x01
#define PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0x10
#define PLL_VIDEO2_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5
#define PLL_VIDEO2_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK 0x00000020
#define PLL_VIDEO2_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0x0
#define PLL_VIDEO2_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0x1
#define PLL_VIDEO2_CTRL_REG_PLL_INPUT_DIV2_OFFSET 1
#define PLL_VIDEO2_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK 0x00000002
#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET 0
#define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK 0x00000001

#define PLL_VE_CTRL_REG 0x00000058//PLL_VE Control Register
#define PLL_VE_CTRL_REG_PLL_EN_OFFSET 31
#define PLL_VE_CTRL_REG_PLL_EN_CLEAR_MASK 0x80000000
#define PLL_VE_CTRL_REG_PLL_EN_DISABLE 0x0
#define PLL_VE_CTRL_REG_PLL_EN_ENABLE 0x1
#define PLL_VE_CTRL_REG_PLL_LDO_EN_OFFSET 30
#define PLL_VE_CTRL_REG_PLL_LDO_EN_CLEAR_MASK 0x40000000
#define PLL_VE_CTRL_REG_PLL_LDO_EN_DISABLE 0x0
#define PLL_VE_CTRL_REG_PLL_LDO_EN_ENABLE 0x1
#define PLL_VE_CTRL_REG_LOCK_ENABLE_OFFSET 29
#define PLL_VE_CTRL_REG_LOCK_ENABLE_CLEAR_MASK 0x20000000
#define PLL_VE_CTRL_REG_LOCK_ENABLE_DISABLE 0x0
#define PLL_VE_CTRL_REG_LOCK_ENABLE_ENABLE 0x1
#define PLL_VE_CTRL_REG_LOCK_OFFSET 28
#define PLL_VE_CTRL_REG_LOCK_CLEAR_MASK 0x10000000
#define PLL_VE_CTRL_REG_LOCK_UNLOCKED 0x0
#define PLL_VE_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0x1
#define PLL_VE_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27
#define PLL_VE_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK 0x08000000
#define PLL_VE_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0x0
#define PLL_VE_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0x1
#define PLL_VE_CTRL_REG_PLL_SDM_EN_OFFSET 24
#define PLL_VE_CTRL_REG_PLL_SDM_EN_CLEAR_MASK 0x01000000
#define PLL_VE_CTRL_REG_PLL_SDM_EN_DISABLE 0x0
#define PLL_VE_CTRL_REG_PLL_SDM_EN_ENABLE 0x1
#define PLL_VE_CTRL_REG_PLL_N_OFFSET 8
#define PLL_VE_CTRL_REG_PLL_N_CLEAR_MASK 0x0000ff00
#define PLL_VE_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6
#define PLL_VE_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK 0x000000c0
#define PLL_VE_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0x00
#define PLL_VE_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0x01
#define PLL_VE_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0x10
#define PLL_VE_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5
#define PLL_VE_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK 0x00000020
#define PLL_VE_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0x0
#define PLL_VE_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0x1
#define PLL_VE_CTRL_REG_PLL_INPUT_DIV2_OFFSET 1
#define PLL_VE_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK 0x00000002
#define PLL_VE_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET 0
#define PLL_VE_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK 0x00000001

#define PLL_VIDEO3_CTRL_REG 0x00000068//PLL_VIDEO3 Control Register
#define PLL_VIDEO3_CTRL_REG_PLL_EN_OFFSET 31
#define PLL_VIDEO3_CTRL_REG_PLL_EN_CLEAR_MASK 0x80000000
#define PLL_VIDEO3_CTRL_REG_PLL_EN_DISABLE 0x0
#define PLL_VIDEO3_CTRL_REG_PLL_EN_ENABLE 0x1
#define PLL_VIDEO3_CTRL_REG_PLL_LDO_EN_OFFSET 30
#define PLL_VIDEO3_CTRL_REG_PLL_LDO_EN_CLEAR_MASK 0x40000000
#define PLL_VIDEO3_CTRL_REG_PLL_LDO_EN_DISABLE 0x0
#define PLL_VIDEO3_CTRL_REG_PLL_LDO_EN_ENABLE 0x1
#define PLL_VIDEO3_CTRL_REG_LOCK_ENABLE_OFFSET 29
#define PLL_VIDEO3_CTRL_REG_LOCK_ENABLE_CLEAR_MASK 0x20000000
#define PLL_VIDEO3_CTRL_REG_LOCK_ENABLE_DISABLE 0x0
#define PLL_VIDEO3_CTRL_REG_LOCK_ENABLE_ENABLE 0x1
#define PLL_VIDEO3_CTRL_REG_LOCK_OFFSET 28
#define PLL_VIDEO3_CTRL_REG_LOCK_CLEAR_MASK 0x10000000
#define PLL_VIDEO3_CTRL_REG_LOCK_UNLOCKED 0x0
#define PLL_VIDEO3_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0x1
#define PLL_VIDEO3_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27
#define PLL_VIDEO3_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK 0x08000000
#define PLL_VIDEO3_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0x0
#define PLL_VIDEO3_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0x1
#define PLL_VIDEO3_CTRL_REG_PLL_SDM_EN_OFFSET 24
#define PLL_VIDEO3_CTRL_REG_PLL_SDM_EN_CLEAR_MASK 0x01000000
#define PLL_VIDEO3_CTRL_REG_PLL_SDM_EN_DISABLE 0x0
#define PLL_VIDEO3_CTRL_REG_PLL_SDM_EN_ENABLE 0x1
#define PLL_VIDEO3_CTRL_REG_PLL_N_OFFSET 8
#define PLL_VIDEO3_CTRL_REG_PLL_N_CLEAR_MASK 0x0000ff00
#define PLL_VIDEO3_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6
#define PLL_VIDEO3_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK 0x000000c0
#define PLL_VIDEO3_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0x00
#define PLL_VIDEO3_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0x01
#define PLL_VIDEO3_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0x10
#define PLL_VIDEO3_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5
#define PLL_VIDEO3_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK 0x00000020
#define PLL_VIDEO3_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0x0
#define PLL_VIDEO3_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0x1
#define PLL_VIDEO3_CTRL_REG_PLL_INPUT_DIV2_OFFSET 1
#define PLL_VIDEO3_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK 0x00000002
#define PLL_VIDEO3_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET 0
#define PLL_VIDEO3_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK 0x00000001

#define PLL_AUDIO_CTRL_REG 0x00000078//PLL_AUDIO Control Register
#define PLL_AUDIO_CTRL_REG_PLL_EN_OFFSET 31
#define PLL_AUDIO_CTRL_REG_PLL_EN_CLEAR_MASK 0x80000000
#define PLL_AUDIO_CTRL_REG_PLL_EN_DISABLE 0x0
#define PLL_AUDIO_CTRL_REG_PLL_EN_ENABLE 0x1
#define PLL_AUDIO_CTRL_REG_PLL_LDO_EN_OFFSET 30
#define PLL_AUDIO_CTRL_REG_PLL_LDO_EN_CLEAR_MASK 0x40000000
#define PLL_AUDIO_CTRL_REG_PLL_LDO_EN_DISABLE 0x0
#define PLL_AUDIO_CTRL_REG_PLL_LDO_EN_ENABLE 0x1
#define PLL_AUDIO_CTRL_REG_LOCK_ENABLE_OFFSET 29
#define PLL_AUDIO_CTRL_REG_LOCK_ENABLE_CLEAR_MASK 0x20000000
#define PLL_AUDIO_CTRL_REG_LOCK_ENABLE_DISABLE 0x0
#define PLL_AUDIO_CTRL_REG_LOCK_ENABLE_ENABLE 0x1
#define PLL_AUDIO_CTRL_REG_LOCK_OFFSET 28
#define PLL_AUDIO_CTRL_REG_LOCK_CLEAR_MASK 0x10000000
#define PLL_AUDIO_CTRL_REG_LOCK_UNLOCKED 0x0
#define PLL_AUDIO_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0x1
#define PLL_AUDIO_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27
#define PLL_AUDIO_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK 0x08000000
#define PLL_AUDIO_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0x0
#define PLL_AUDIO_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0x1
#define PLL_AUDIO_CTRL_REG_PLL_SDM_EN_OFFSET 24
#define PLL_AUDIO_CTRL_REG_PLL_SDM_EN_CLEAR_MASK 0x01000000
#define PLL_AUDIO_CTRL_REG_PLL_SDM_EN_DISABLE 0x0
#define PLL_AUDIO_CTRL_REG_PLL_SDM_EN_ENABLE 0x1
#define PLL_AUDIO_CTRL_REG_PLL_P_OFFSET 16
#define PLL_AUDIO_CTRL_REG_PLL_P_CLEAR_MASK 0x003f0000
#define PLL_AUDIO_CTRL_REG_PLL_N_OFFSET 8
#define PLL_AUDIO_CTRL_REG_PLL_N_CLEAR_MASK 0x0000ff00
#define PLL_AUDIO_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6
#define PLL_AUDIO_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK 0x000000c0
#define PLL_AUDIO_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0x00
#define PLL_AUDIO_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0x01
#define PLL_AUDIO_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0x10
#define PLL_AUDIO_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5
#define PLL_AUDIO_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK 0x00000020
#define PLL_AUDIO_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0x0
#define PLL_AUDIO_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0x1
#define PLL_AUDIO_CTRL_REG_PLL_INPUT_DIV2_OFFSET 1
#define PLL_AUDIO_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK 0x00000002
#define PLL_AUDIO_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET 0
#define PLL_AUDIO_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK 0x00000001

#define PLL_NPU_CTRL_REG 0x00000080//PLL_NPU Control Register
#define PLL_NPU_CTRL_REG_PLL_EN_OFFSET 31
#define PLL_NPU_CTRL_REG_PLL_EN_CLEAR_MASK 0x80000000
#define PLL_NPU_CTRL_REG_PLL_EN_DISABLE 0x0
#define PLL_NPU_CTRL_REG_PLL_EN_ENABLE 0x1
#define PLL_NPU_CTRL_REG_PLL_LDO_EN_OFFSET 30
#define PLL_NPU_CTRL_REG_PLL_LDO_EN_CLEAR_MASK 0x40000000
#define PLL_NPU_CTRL_REG_PLL_LDO_EN_DISABLE 0x0
#define PLL_NPU_CTRL_REG_PLL_LDO_EN_ENABLE 0x1
#define PLL_NPU_CTRL_REG_LOCK_ENABLE_OFFSET 29
#define PLL_NPU_CTRL_REG_LOCK_ENABLE_CLEAR_MASK 0x20000000
#define PLL_NPU_CTRL_REG_LOCK_ENABLE_DISABLE 0x0
#define PLL_NPU_CTRL_REG_LOCK_ENABLE_ENABLE 0x1
#define PLL_NPU_CTRL_REG_LOCK_OFFSET 28
#define PLL_NPU_CTRL_REG_LOCK_CLEAR_MASK 0x10000000
#define PLL_NPU_CTRL_REG_LOCK_UNLOCKED 0x0
#define PLL_NPU_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0x1
#define PLL_NPU_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27
#define PLL_NPU_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK 0x08000000
#define PLL_NPU_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0x0
#define PLL_NPU_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0x1
#define PLL_NPU_CTRL_REG_PLL_SDM_EN_OFFSET 24
#define PLL_NPU_CTRL_REG_PLL_SDM_EN_CLEAR_MASK 0x01000000
#define PLL_NPU_CTRL_REG_PLL_SDM_EN_DISABLE 0x0
#define PLL_NPU_CTRL_REG_PLL_SDM_EN_ENABLE 0x1
#define PLL_NPU_CTRL_REG_PLL_N_OFFSET 8
#define PLL_NPU_CTRL_REG_PLL_N_CLEAR_MASK 0x0000ff00
#define PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6
#define PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK 0x000000c0
#define PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0x00
#define PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0x01
#define PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0x10
#define PLL_NPU_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5
#define PLL_NPU_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK 0x00000020
#define PLL_NPU_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0x0
#define PLL_NPU_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0x1
#define PLL_NPU_CTRL_REG_PLL_INPUT_DIV2_OFFSET 1
#define PLL_NPU_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK 0x00000002
#define PLL_NPU_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET 0
#define PLL_NPU_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK 0x00000001

#define PLL_DDR_PAT0_CTRL_REG 0x00000110//PLL_DDR Pattern0 Control Register
#define PLL_DDR_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31
#define PLL_DDR_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK 0x80000000
#define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29
#define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK 0x60000000
#define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0 0x00
#define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1 0x01
#define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0x10
#define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT 0x11
#define PLL_DDR_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20
#define PLL_DDR_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK 0x1ff00000
#define PLL_DDR_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET 19
#define PLL_DDR_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK 0x00080000
#define PLL_DDR_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ 0x0
#define PLL_DDR_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ 0x1
#define PLL_DDR_PAT0_CTRL_REG_FREQ_OFFSET 17
#define PLL_DDR_PAT0_CTRL_REG_FREQ_CLEAR_MASK 0x00060000
#define PLL_DDR_PAT0_CTRL_REG_FREQ_31_5KHZ 0x00
#define PLL_DDR_PAT0_CTRL_REG_FREQ_32KHZ 0x01
#define PLL_DDR_PAT0_CTRL_REG_FREQ_32_5KHZ 0x10
#define PLL_DDR_PAT0_CTRL_REG_FREQ_33KHZ 0x11
#define PLL_DDR_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0
#define PLL_DDR_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK 0x0001ffff

#define PLL_DDR_PAT1_CTRL_REG 0x00000114//PLL_DDR Pattern1 Control Register
#define PLL_DDR_PAT1_CTRL_REG_DITHER_EN_OFFSET 24
#define PLL_DDR_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK 0x01000000
#define PLL_DDR_PAT1_CTRL_REG_FRAC_EN_OFFSET 20
#define PLL_DDR_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK 0x00100000
#define PLL_DDR_PAT1_CTRL_REG_FRAC_IN_OFFSET 0
#define PLL_DDR_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK 0x0001ffff

#define PLL_PERI0_PAT0_CTRL_REG 0x00000120//PLL_PERI0 Pattern0 Control Register
#define PLL_PERI0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31
#define PLL_PERI0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK 0x80000000
#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29
#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK 0x60000000
#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0 0x00
#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1 0x01
#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0x10
#define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT 0x11
#define PLL_PERI0_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20
#define PLL_PERI0_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK 0x1ff00000
#define PLL_PERI0_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET 19
#define PLL_PERI0_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK 0x00080000
#define PLL_PERI0_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ 0x0
#define PLL_PERI0_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ 0x1
#define PLL_PERI0_PAT0_CTRL_REG_FREQ_OFFSET 17
#define PLL_PERI0_PAT0_CTRL_REG_FREQ_CLEAR_MASK 0x00060000
#define PLL_PERI0_PAT0_CTRL_REG_FREQ_31_5KHZ 0x00
#define PLL_PERI0_PAT0_CTRL_REG_FREQ_32KHZ 0x01
#define PLL_PERI0_PAT0_CTRL_REG_FREQ_32_5KHZ 0x10
#define PLL_PERI0_PAT0_CTRL_REG_FREQ_33KHZ 0x11
#define PLL_PERI0_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0
#define PLL_PERI0_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK 0x0001ffff

#define PLL_PERI0_PAT1_CTRL_REG 0x00000124//PLL_PERI0 Pattern1 Control Register
#define PLL_PERI0_PAT1_CTRL_REG_DITHER_EN_OFFSET 24
#define PLL_PERI0_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK 0x01000000
#define PLL_PERI0_PAT1_CTRL_REG_FRAC_EN_OFFSET 20
#define PLL_PERI0_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK 0x00100000
#define PLL_PERI0_PAT1_CTRL_REG_FRAC_IN_OFFSET 0
#define PLL_PERI0_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK 0x0001ffff

#define PLL_PERI1_PAT0_CTRL_REG 0x00000128//PLL_PERI1 Pattern0 Control Register
#define PLL_PERI1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31
#define PLL_PERI1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK 0x80000000
#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29
#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK 0x60000000
#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0 0x00
#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1 0x01
#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0x10
#define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT 0x11
#define PLL_PERI1_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20
#define PLL_PERI1_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK 0x1ff00000
#define PLL_PERI1_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET 19
#define PLL_PERI1_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK 0x00080000
#define PLL_PERI1_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ 0x0
#define PLL_PERI1_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ 0x1
#define PLL_PERI1_PAT0_CTRL_REG_FREQ_OFFSET 17
#define PLL_PERI1_PAT0_CTRL_REG_FREQ_CLEAR_MASK 0x00060000
#define PLL_PERI1_PAT0_CTRL_REG_FREQ_31_5KHZ 0x00
#define PLL_PERI1_PAT0_CTRL_REG_FREQ_32KHZ 0x01
#define PLL_PERI1_PAT0_CTRL_REG_FREQ_32_5KHZ 0x10
#define PLL_PERI1_PAT0_CTRL_REG_FREQ_33KHZ 0x11
#define PLL_PERI1_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0
#define PLL_PERI1_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK 0x0001ffff

#define PLL_PERI1_PAT1_CTRL_REG 0x0000012c//PLL_PERI1 Pattern1 Control Register
#define PLL_PERI1_PAT1_CTRL_REG_DITHER_EN_OFFSET 24
#define PLL_PERI1_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK 0x01000000
#define PLL_PERI1_PAT1_CTRL_REG_FRAC_EN_OFFSET 20
#define PLL_PERI1_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK 0x00100000
#define PLL_PERI1_PAT1_CTRL_REG_FRAC_IN_OFFSET 0
#define PLL_PERI1_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK 0x0001ffff

#define PLL_GPU_PAT0_CTRL_REG 0x00000130//PLL_GPU Pattern0 Control Register
#define PLL_GPU_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31
#define PLL_GPU_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK 0x80000000
#define PLL_GPU_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29
#define PLL_GPU_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK 0x60000000
#define PLL_GPU_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0 0x00
#define PLL_GPU_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1 0x01
#define PLL_GPU_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0x10
#define PLL_GPU_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT 0x11
#define PLL_GPU_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20
#define PLL_GPU_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK 0x1ff00000
#define PLL_GPU_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET 19
#define PLL_GPU_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK 0x00080000
#define PLL_GPU_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ 0x0
#define PLL_GPU_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ 0x1
#define PLL_GPU_PAT0_CTRL_REG_FREQ_OFFSET 17
#define PLL_GPU_PAT0_CTRL_REG_FREQ_CLEAR_MASK 0x00060000
#define PLL_GPU_PAT0_CTRL_REG_FREQ_31_5KHZ 0x00
#define PLL_GPU_PAT0_CTRL_REG_FREQ_32KHZ 0x01
#define PLL_GPU_PAT0_CTRL_REG_FREQ_32_5KHZ 0x10
#define PLL_GPU_PAT0_CTRL_REG_FREQ_33KHZ 0x11
#define PLL_GPU_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0
#define PLL_GPU_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK 0x0001ffff

#define PLL_GPU_PAT1_CTRL_REG 0x00000134//PLL_GPU Pattern1 Control Register
#define PLL_GPU_PAT1_CTRL_REG_DITHER_EN_OFFSET 24
#define PLL_GPU_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK 0x01000000
#define PLL_GPU_PAT1_CTRL_REG_FRAC_EN_OFFSET 20
#define PLL_GPU_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK 0x00100000
#define PLL_GPU_PAT1_CTRL_REG_FRAC_IN_OFFSET 0
#define PLL_GPU_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK 0x0001ffff

#define PLL_VIDEO0_PAT0_CTRL_REG 0x00000140//PLL_VIDEO0 Pattern0 Control Register
#define PLL_VIDEO0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31
#define PLL_VIDEO0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK 0x80000000
#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29
#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK 0x60000000
#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0 0x00
#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1 0x01
#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0x10
#define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT 0x11
#define PLL_VIDEO0_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20
#define PLL_VIDEO0_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK 0x1ff00000
#define PLL_VIDEO0_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET 19
#define PLL_VIDEO0_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK 0x00080000
#define PLL_VIDEO0_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ 0x0
#define PLL_VIDEO0_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ 0x1
#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_OFFSET 17
#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_CLEAR_MASK 0x00060000
#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_31_5KHZ 0x00
#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_32KHZ 0x01
#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_32_5KHZ 0x10
#define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_33KHZ 0x11
#define PLL_VIDEO0_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0
#define PLL_VIDEO0_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK 0x0001ffff

#define PLL_VIDEO0_PAT1_CTRL_REG 0x00000144//PLL_VIDEO0 Pattern1 Control Register
#define PLL_VIDEO0_PAT1_CTRL_REG_DITHER_EN_OFFSET 24
#define PLL_VIDEO0_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK 0x01000000
#define PLL_VIDEO0_PAT1_CTRL_REG_FRAC_EN_OFFSET 20
#define PLL_VIDEO0_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK 0x00100000
#define PLL_VIDEO0_PAT1_CTRL_REG_FRAC_IN_OFFSET 0
#define PLL_VIDEO0_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK 0x0001ffff

#define PLL_VIDEO1_PAT0_CTRL_REG 0x00000148//PLL_VIDEO1 Pattern0 Control Register
#define PLL_VIDEO1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31
#define PLL_VIDEO1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK 0x80000000
#define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29
#define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK 0x60000000
#define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0 0x00
#define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1 0x01
#define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0x10
#define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT 0x11
#define PLL_VIDEO1_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20
#define PLL_VIDEO1_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK 0x1ff00000
#define PLL_VIDEO1_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET 19
#define PLL_VIDEO1_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK 0x00080000
#define PLL_VIDEO1_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ 0x0
#define PLL_VIDEO1_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ 0x1
#define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_OFFSET 17
#define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_CLEAR_MASK 0x00060000
#define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_31_5KHZ 0x00
#define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_32KHZ 0x01
#define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_32_5KHZ 0x10
#define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_33KHZ 0x11
#define PLL_VIDEO1_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0
#define PLL_VIDEO1_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK 0x0001ffff

#define PLL_VIDEO1_PAT1_CTRL_REG 0x0000014c//PLL_VIDEO1 Pattern1 Control Register
#define PLL_VIDEO1_PAT1_CTRL_REG_DITHER_EN_OFFSET 24
#define PLL_VIDEO1_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK 0x01000000
#define PLL_VIDEO1_PAT1_CTRL_REG_FRAC_EN_OFFSET 20
#define PLL_VIDEO1_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK 0x00100000
#define PLL_VIDEO1_PAT1_CTRL_REG_FRAC_IN_OFFSET 0
#define PLL_VIDEO1_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK 0x0001ffff

#define PLL_VIDEO2_PAT0_CTRL_REG 0x00000150//PLL_VIDEO2 Pattern0 Control Register
#define PLL_VIDEO2_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31
#define PLL_VIDEO2_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK 0x80000000
#define PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29
#define PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK 0x60000000
#define PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0 0x00
#define PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1 0x01
#define PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0x10
#define PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT 0x11
#define PLL_VIDEO2_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20
#define PLL_VIDEO2_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK 0x1ff00000
#define PLL_VIDEO2_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET 19
#define PLL_VIDEO2_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK 0x00080000
#define PLL_VIDEO2_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ 0x0
#define PLL_VIDEO2_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ 0x1
#define PLL_VIDEO2_PAT0_CTRL_REG_FREQ_OFFSET 17
#define PLL_VIDEO2_PAT0_CTRL_REG_FREQ_CLEAR_MASK 0x00060000
#define PLL_VIDEO2_PAT0_CTRL_REG_FREQ_31_5KHZ 0x00
#define PLL_VIDEO2_PAT0_CTRL_REG_FREQ_32KHZ 0x01
#define PLL_VIDEO2_PAT0_CTRL_REG_FREQ_32_5KHZ 0x10
#define PLL_VIDEO2_PAT0_CTRL_REG_FREQ_33KHZ 0x11
#define PLL_VIDEO2_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0
#define PLL_VIDEO2_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK 0x0001ffff

#define PLL_VIDEO2_PAT1_CTRL_REG 0x00000154//PLL_VIDEO2 Pattern1 Control Register
#define PLL_VIDEO2_PAT1_CTRL_REG_DITHER_EN_OFFSET 24
#define PLL_VIDEO2_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK 0x01000000
#define PLL_VIDEO2_PAT1_CTRL_REG_FRAC_EN_OFFSET 20
#define PLL_VIDEO2_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK 0x00100000
#define PLL_VIDEO2_PAT1_CTRL_REG_FRAC_IN_OFFSET 0
#define PLL_VIDEO2_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK 0x0001ffff

#define PLL_VE_PAT0_CTRL_REG 0x00000158//PLL_VE Pattern0 Control Register
#define PLL_VE_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31
#define PLL_VE_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK 0x80000000
#define PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29
#define PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK 0x60000000
#define PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0 0x00
#define PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1 0x01
#define PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0x10
#define PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT 0x11
#define PLL_VE_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20
#define PLL_VE_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK 0x1ff00000
#define PLL_VE_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET 19
#define PLL_VE_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK 0x00080000
#define PLL_VE_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ 0x0
#define PLL_VE_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ 0x1
#define PLL_VE_PAT0_CTRL_REG_FREQ_OFFSET 17
#define PLL_VE_PAT0_CTRL_REG_FREQ_CLEAR_MASK 0x00060000
#define PLL_VE_PAT0_CTRL_REG_FREQ_31_5KHZ 0x00
#define PLL_VE_PAT0_CTRL_REG_FREQ_32KHZ 0x01
#define PLL_VE_PAT0_CTRL_REG_FREQ_32_5KHZ 0x10
#define PLL_VE_PAT0_CTRL_REG_FREQ_33KHZ 0x11
#define PLL_VE_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0
#define PLL_VE_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK 0x0001ffff

#define PLL_VE_PAT1_CTRL_REG 0x0000015c//PLL_VE Pattern1 Control Register
#define PLL_VE_PAT1_CTRL_REG_DITHER_EN_OFFSET 24
#define PLL_VE_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK 0x01000000
#define PLL_VE_PAT1_CTRL_REG_FRAC_EN_OFFSET 20
#define PLL_VE_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK 0x00100000
#define PLL_VE_PAT1_CTRL_REG_FRAC_IN_OFFSET 0
#define PLL_VE_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK 0x0001ffff

#define PLL_VIDEO3_PAT0_CTRL_REG 0x00000168//PLL_VIDEO3 Pattern0 Control Register
#define PLL_VIDEO3_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31
#define PLL_VIDEO3_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK 0x80000000
#define PLL_VIDEO3_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29
#define PLL_VIDEO3_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK 0x60000000
#define PLL_VIDEO3_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0 0x00
#define PLL_VIDEO3_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1 0x01
#define PLL_VIDEO3_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0x10
#define PLL_VIDEO3_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT 0x11
#define PLL_VIDEO3_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20
#define PLL_VIDEO3_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK 0x1ff00000
#define PLL_VIDEO3_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET 19
#define PLL_VIDEO3_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK 0x00080000
#define PLL_VIDEO3_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ 0x0
#define PLL_VIDEO3_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ 0x1
#define PLL_VIDEO3_PAT0_CTRL_REG_FREQ_OFFSET 17
#define PLL_VIDEO3_PAT0_CTRL_REG_FREQ_CLEAR_MASK 0x00060000
#define PLL_VIDEO3_PAT0_CTRL_REG_FREQ_31_5KHZ 0x00
#define PLL_VIDEO3_PAT0_CTRL_REG_FREQ_32KHZ 0x01
#define PLL_VIDEO3_PAT0_CTRL_REG_FREQ_32_5KHZ 0x10
#define PLL_VIDEO3_PAT0_CTRL_REG_FREQ_33KHZ 0x11
#define PLL_VIDEO3_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0
#define PLL_VIDEO3_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK 0x0001ffff

#define PLL_VIDEO3_PAT1_CTRL_REG 0x0000016c//PLL_VIDEO3 Pattern1 Control Register
#define PLL_VIDEO3_PAT1_CTRL_REG_DITHER_EN_OFFSET 24
#define PLL_VIDEO3_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK 0x01000000
#define PLL_VIDEO3_PAT1_CTRL_REG_FRAC_EN_OFFSET 20
#define PLL_VIDEO3_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK 0x00100000
#define PLL_VIDEO3_PAT1_CTRL_REG_FRAC_IN_OFFSET 0
#define PLL_VIDEO3_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK 0x0001ffff

#define PLL_AUDIO_PAT0_CTRL_REG 0x00000178//PLL_AUDIO Pattern0 Control Register
#define PLL_AUDIO_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31
#define PLL_AUDIO_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK 0x80000000
#define PLL_AUDIO_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29
#define PLL_AUDIO_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK 0x60000000
#define PLL_AUDIO_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0 0x00
#define PLL_AUDIO_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1 0x01
#define PLL_AUDIO_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0x10
#define PLL_AUDIO_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT 0x11
#define PLL_AUDIO_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20
#define PLL_AUDIO_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK 0x1ff00000
#define PLL_AUDIO_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET 19
#define PLL_AUDIO_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK 0x00080000
#define PLL_AUDIO_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ 0x0
#define PLL_AUDIO_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ 0x1
#define PLL_AUDIO_PAT0_CTRL_REG_FREQ_OFFSET 17
#define PLL_AUDIO_PAT0_CTRL_REG_FREQ_CLEAR_MASK 0x00060000
#define PLL_AUDIO_PAT0_CTRL_REG_FREQ_31_5KHZ 0x00
#define PLL_AUDIO_PAT0_CTRL_REG_FREQ_32KHZ 0x01
#define PLL_AUDIO_PAT0_CTRL_REG_FREQ_32_5KHZ 0x10
#define PLL_AUDIO_PAT0_CTRL_REG_FREQ_33KHZ 0x11
#define PLL_AUDIO_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0
#define PLL_AUDIO_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK 0x0001ffff

#define PLL_AUDIO_PAT1_CTRL_REG 0x0000017c//PLL_AUDIO Pattern1 Control Register
#define PLL_AUDIO_PAT1_CTRL_REG_DITHER_EN_OFFSET 24
#define PLL_AUDIO_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK 0x01000000
#define PLL_AUDIO_PAT1_CTRL_REG_FRAC_EN_OFFSET 20
#define PLL_AUDIO_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK 0x00100000
#define PLL_AUDIO_PAT1_CTRL_REG_FRAC_IN_OFFSET 0
#define PLL_AUDIO_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK 0x0001ffff

#define PLL_NPU_PAT0_CTRL_REG 0x00000180//PLL_NPU Pattern0 Control Register
#define PLL_NPU_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31
#define PLL_NPU_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK 0x80000000
#define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29
#define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK 0x60000000
#define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0 0x00
#define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1 0x01
#define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0x10
#define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT 0x11
#define PLL_NPU_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20
#define PLL_NPU_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK 0x1ff00000
#define PLL_NPU_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET 19
#define PLL_NPU_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK 0x00080000
#define PLL_NPU_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ 0x0
#define PLL_NPU_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ 0x1
#define PLL_NPU_PAT0_CTRL_REG_FREQ_OFFSET 17
#define PLL_NPU_PAT0_CTRL_REG_FREQ_CLEAR_MASK 0x00060000
#define PLL_NPU_PAT0_CTRL_REG_FREQ_31_5KHZ 0x00
#define PLL_NPU_PAT0_CTRL_REG_FREQ_32KHZ 0x01
#define PLL_NPU_PAT0_CTRL_REG_FREQ_32_5KHZ 0x10
#define PLL_NPU_PAT0_CTRL_REG_FREQ_33KHZ 0x11
#define PLL_NPU_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0
#define PLL_NPU_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK 0x0001ffff

#define PLL_NPU_PAT1_CTRL_REG 0x00000184//PLL_NPU Pattern1 Control Register
#define PLL_NPU_PAT1_CTRL_REG_DITHER_EN_OFFSET 24
#define PLL_NPU_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK 0x01000000
#define PLL_NPU_PAT1_CTRL_REG_FRAC_EN_OFFSET 20
#define PLL_NPU_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK 0x00100000
#define PLL_NPU_PAT1_CTRL_REG_FRAC_IN_OFFSET 0
#define PLL_NPU_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK 0x0001ffff

#define PLL_CPU0_BIAS_REG 0x00000300//PLL_CPU0 Bias Register
#define PLL_CPU0_BIAS_REG_PLL_VCO_RST_IN_OFFSET 31
#define PLL_CPU0_BIAS_REG_PLL_VCO_RST_IN_CLEAR_MASK 0x80000000
#define PLL_CPU0_BIAS_REG_PLL_CP_OFFSET 16
#define PLL_CPU0_BIAS_REG_PLL_CP_CLEAR_MASK 0x001f0000

#define PLL_CPU1_BIAS_REG 0x00000308//PLL_CPU1 Bias Register
#define PLL_CPU1_BIAS_REG_PLL_VCO_RST_IN_OFFSET 31
#define PLL_CPU1_BIAS_REG_PLL_VCO_RST_IN_CLEAR_MASK 0x80000000
#define PLL_CPU1_BIAS_REG_PLL_CP_OFFSET 16
#define PLL_CPU1_BIAS_REG_PLL_CP_CLEAR_MASK 0x001f0000

#define PLL_CPU2_BIAS_REG 0x0000030c//PLL_CPU2 Bias Register
#define PLL_CPU2_BIAS_REG_PLL_VCO_RST_IN_OFFSET 31
#define PLL_CPU2_BIAS_REG_PLL_VCO_RST_IN_CLEAR_MASK 0x80000000
#define PLL_CPU2_BIAS_REG_PLL_CP_OFFSET 16
#define PLL_CPU2_BIAS_REG_PLL_CP_CLEAR_MASK 0x001f0000

#define PLL_DDR_BIAS_REG 0x00000310//PLL_DDR Bias Register
#define PLL_DDR_BIAS_REG_PLL_CP_OFFSET 16
#define PLL_DDR_BIAS_REG_PLL_CP_CLEAR_MASK 0x001f0000

#define PLL_PERI0_BIAS_REG 0x00000320//PLL_PERI0 Bias Register
#define PLL_PERI0_BIAS_REG_PLL_CP_OFFSET 16
#define PLL_PERI0_BIAS_REG_PLL_CP_CLEAR_MASK 0x001f0000

#define PLL_PERI1_BIAS_REG 0x00000328//PLL_PERI1 Bias Register
#define PLL_PERI1_BIAS_REG_PLL_CP_OFFSET 16
#define PLL_PERI1_BIAS_REG_PLL_CP_CLEAR_MASK 0x001f0000

#define PLL_GPU_BIAS_REG 0x00000330//PLL_GPU Bias Register
#define PLL_GPU_BIAS_REG_PLL_CP_OFFSET 16
#define PLL_GPU_BIAS_REG_PLL_CP_CLEAR_MASK 0x001f0000

#define PLL_VIDEO0_BIAS_REG 0x00000340//PLL_VIDEO0 Bias Register
#define PLL_VIDEO0_BIAS_REG_PLL_CP_OFFSET 16
#define PLL_VIDEO0_BIAS_REG_PLL_CP_CLEAR_MASK 0x001f0000

#define PLL_VIDEO1_BIAS_REG 0x00000348//PLL_VIDEO1 Bias Register
#define PLL_VIDEO1_BIAS_REG_PLL_CP_OFFSET 16
#define PLL_VIDEO1_BIAS_REG_PLL_CP_CLEAR_MASK 0x001f0000

#define PLL_VIDEO2_BIAS_REG 0x00000350//PLL_VIDEO2 Bias Register
#define PLL_VIDEO2_BIAS_REG_PLL_CP_OFFSET 16
#define PLL_VIDEO2_BIAS_REG_PLL_CP_CLEAR_MASK 0x001f0000

#define PLL_VE_BIAS_REG 0x00000358//PLL_VE Bias Register
#define PLL_VE_BIAS_REG_PLL_CP_OFFSET 16
#define PLL_VE_BIAS_REG_PLL_CP_CLEAR_MASK 0x001f0000

#define PLL_VIDEO3_BIAS_REG 0x00000368//PLL_VIDEO3 Bias Register
#define PLL_VIDEO3_BIAS_REG_PLL_CP_OFFSET 16
#define PLL_VIDEO3_BIAS_REG_PLL_CP_CLEAR_MASK 0x001f0000

#define PLL_AUDIO_BIAS_REG 0x00000378//PLL_AUDIO Bias Register
#define PLL_AUDIO_BIAS_REG_PLL_CP_OFFSET 16
#define PLL_AUDIO_BIAS_REG_PLL_CP_CLEAR_MASK 0x001f0000

#define PLL_NPU_BIAS_REG 0x00000380//PLL_NPU Bias Register
#define PLL_NPU_BIAS_REG_PLL_CP_OFFSET 16
#define PLL_NPU_BIAS_REG_PLL_CP_CLEAR_MASK 0x001f0000

#define PLL_CPU0_TUN_REG 0x00000400//PLL_CPU0 Tuning Register
#define PLL_CPU0_TUN_REG_PLL_VCO_OFFSET 28
#define PLL_CPU0_TUN_REG_PLL_VCO_CLEAR_MASK 0x70000000
#define PLL_CPU0_TUN_REG_PLL_VCO_GAIN_OFFSET 24
#define PLL_CPU0_TUN_REG_PLL_VCO_GAIN_CLEAR_MASK 0x07000000
#define PLL_CPU0_TUN_REG_PLL_CNT_INT_OFFSET 16
#define PLL_CPU0_TUN_REG_PLL_CNT_INT_CLEAR_MASK 0x007f0000
#define PLL_CPU0_TUN_REG_PLL_REG_OD_OFFSET 15
#define PLL_CPU0_TUN_REG_PLL_REG_OD_CLEAR_MASK 0x00008000
#define PLL_CPU0_TUN_REG_PLL_B_IN_OFFSET 8
#define PLL_CPU0_TUN_REG_PLL_B_IN_CLEAR_MASK 0x00007f00
#define PLL_CPU0_TUN_REG_PLL_REG_OD1_OFFSET 7
#define PLL_CPU0_TUN_REG_PLL_REG_OD1_CLEAR_MASK 0x00000080
#define PLL_CPU0_TUN_REG_PLL_B_OUT_OFFSET 0
#define PLL_CPU0_TUN_REG_PLL_B_OUT_CLEAR_MASK 0x0000007f

#define PLL_CPU1_TUN_REG 0x00000408//PLL_CPU1 Tuning Register
#define PLL_CPU1_TUN_REG_PLL_VCO_OFFSET 28
#define PLL_CPU1_TUN_REG_PLL_VCO_CLEAR_MASK 0x70000000
#define PLL_CPU1_TUN_REG_PLL_VCO_GAIN_OFFSET 24
#define PLL_CPU1_TUN_REG_PLL_VCO_GAIN_CLEAR_MASK 0x07000000
#define PLL_CPU1_TUN_REG_PLL_CNT_INT_OFFSET 16
#define PLL_CPU1_TUN_REG_PLL_CNT_INT_CLEAR_MASK 0x007f0000
#define PLL_CPU1_TUN_REG_PLL_REG_OD_OFFSET 15
#define PLL_CPU1_TUN_REG_PLL_REG_OD_CLEAR_MASK 0x00008000
#define PLL_CPU1_TUN_REG_PLL_B_IN_OFFSET 8
#define PLL_CPU1_TUN_REG_PLL_B_IN_CLEAR_MASK 0x00007f00
#define PLL_CPU1_TUN_REG_PLL_REG_OD1_OFFSET 7
#define PLL_CPU1_TUN_REG_PLL_REG_OD1_CLEAR_MASK 0x00000080
#define PLL_CPU1_TUN_REG_PLL_B_OUT_OFFSET 0
#define PLL_CPU1_TUN_REG_PLL_B_OUT_CLEAR_MASK 0x0000007f

#define PLL_CPU2_TUN_REG 0x0000040c//PLL_CPU2 Tuning Register
#define PLL_CPU2_TUN_REG_PLL_VCO_OFFSET 28
#define PLL_CPU2_TUN_REG_PLL_VCO_CLEAR_MASK 0x70000000
#define PLL_CPU2_TUN_REG_PLL_VCO_GAIN_OFFSET 24
#define PLL_CPU2_TUN_REG_PLL_VCO_GAIN_CLEAR_MASK 0x07000000
#define PLL_CPU2_TUN_REG_PLL_CNT_INT_OFFSET 16
#define PLL_CPU2_TUN_REG_PLL_CNT_INT_CLEAR_MASK 0x007f0000
#define PLL_CPU2_TUN_REG_PLL_REG_OD_OFFSET 15
#define PLL_CPU2_TUN_REG_PLL_REG_OD_CLEAR_MASK 0x00008000
#define PLL_CPU2_TUN_REG_PLL_B_IN_OFFSET 8
#define PLL_CPU2_TUN_REG_PLL_B_IN_CLEAR_MASK 0x00007f00
#define PLL_CPU2_TUN_REG_PLL_REG_OD1_OFFSET 7
#define PLL_CPU2_TUN_REG_PLL_REG_OD1_CLEAR_MASK 0x00000080
#define PLL_CPU2_TUN_REG_PLL_B_OUT_OFFSET 0
#define PLL_CPU2_TUN_REG_PLL_B_OUT_CLEAR_MASK 0x0000007f

#define CPU_CLK_REG 0x00000500//CPU Clock Register
#define CPU_CLK_REG_CPU_CLK_SEL_OFFSET 24
#define CPU_CLK_REG_CPU_CLK_SEL_CLEAR_MASK 0x07000000
#define CPU_CLK_REG_CPU_CLK_SEL_HOSC 0x000
#define CPU_CLK_REG_CPU_CLK_SEL_CLK32K 0x001
#define CPU_CLK_REG_CPU_CLK_SEL_CLK16M_RC 0x010
#define CPU_CLK_REG_CPU_CLK_SEL_CPU0PLL_P 0x011
#define CPU_CLK_REG_CPU_CLK_SEL_PERI0_600M 0x100
#define CPU_CLK_REG_CPU_CLK_SEL_CPU2PLL 0x101
#define CPU_CLK_REG_PLL_CPU0_OUT_EXT_DIVP_OFFSET 16
#define CPU_CLK_REG_PLL_CPU0_OUT_EXT_DIVP_CLEAR_MASK 0x00030000
#define CPU_CLK_REG_PLL_CPU0_OUT_EXT_DIVP_1 0x00
#define CPU_CLK_REG_PLL_CPU0_OUT_EXT_DIVP_2 0x01
#define CPU_CLK_REG_PLL_CPU0_OUT_EXT_DIVP_4 0x10
#define CPU_CLK_REG_CPU_APB_DIV_CFG_OFFSET 8
#define CPU_CLK_REG_CPU_APB_DIV_CFG_CLEAR_MASK 0x00000300
#define CPU_CLK_REG_CPU_PERI_DIV_CFG_OFFSET 2
#define CPU_CLK_REG_CPU_PERI_DIV_CFG_CLEAR_MASK 0x0000000c
#define CPU_CLK_REG_CPU_PERI_DIV_CFG__M__FACTOR_M1__1 0x1
#define CPU_CLK_REG_CPU_AXI_DIV_CFG_OFFSET 0
#define CPU_CLK_REG_CPU_AXI_DIV_CFG_CLEAR_MASK 0x00000003

#define CPU_GATING_REG 0x00000504//CPU Gating Configuration Register
#define CPU_GATING_REG_CPU_GATING_FIELD_OFFSET 16
#define CPU_GATING_REG_CPU_GATING_FIELD_CLEAR_MASK 0xffff0000
#define CPU_GATING_REG_CPU_GATING_FIELD_0_SIGNAL 0x15
#define CPU_GATING_REG_DSU_CLK_GATING_OFFSET 1
#define CPU_GATING_REG_DSU_CLK_GATING_CLEAR_MASK 0x00000002
#define CPU_GATING_REG_DSU_CLK_GATING_CLOCK_IS_OFF 0x0
#define CPU_GATING_REG_DSU_CLK_GATING_CLOCK_IS_ON 0x1
#define CPU_GATING_REG_CPU0_CLK_GATING_OFFSET 0
#define CPU_GATING_REG_CPU0_CLK_GATING_CLEAR_MASK 0x00000001
#define CPU_GATING_REG_CPU0_CLK_GATING_CLOCK_IS_OFF 0x0
#define CPU_GATING_REG_CPU0_CLK_GATING_CLOCK_IS_ON 0x1

#define TRACE_CLK_REG 0x00000508//TRACE Clock Register
#define TRACE_CLK_REG_TRACE_CLK_GATING_OFFSET 31
#define TRACE_CLK_REG_TRACE_CLK_GATING_CLEAR_MASK 0x80000000
#define TRACE_CLK_REG_TRACE_CLK_GATING_CLOCK_IS_OFF 0x0
#define TRACE_CLK_REG_TRACE_CLK_GATING_CLOCK_IS_ON 0x1
#define TRACE_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define TRACE_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define TRACE_CLK_REG_CLK_SRC_SEL_HOSC 0x000
#define TRACE_CLK_REG_CLK_SRC_SEL_CLK32K 0x001
#define TRACE_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0x010
#define TRACE_CLK_REG_CLK_SRC_SEL_PERI0_300M 0x011
#define TRACE_CLK_REG_CLK_SRC_SEL_PERI0_400M 0x100
#define TRACE_CLK_REG_FACTOR_M_OFFSET 0
#define TRACE_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define DSU_CLK_REG 0x0000050c//DSU Clock Register
#define DSU_CLK_REG_DSU_CLK_SEL_OFFSET 24
#define DSU_CLK_REG_DSU_CLK_SEL_CLEAR_MASK 0x07000000
#define DSU_CLK_REG_DSU_CLK_SEL_HOSC 0x000
#define DSU_CLK_REG_DSU_CLK_SEL_CLK32K 0x001
#define DSU_CLK_REG_DSU_CLK_SEL_CLK16M_RC 0x010
#define DSU_CLK_REG_DSU_CLK_SEL_CPU1PLL_P 0x011
#define DSU_CLK_REG_DSU_CLK_SEL_PERI0PLL2X 0x100
#define DSU_CLK_REG_DSU_CLK_SEL_PERI0_600M 0x101
#define DSU_CLK_REG_PLL_CPU1_OUT_EXT_DIVP_OFFSET 16
#define DSU_CLK_REG_PLL_CPU1_OUT_EXT_DIVP_CLEAR_MASK 0x00030000
#define DSU_CLK_REG_PLL_CPU1_OUT_EXT_DIVP_1 0x00
#define DSU_CLK_REG_PLL_CPU1_OUT_EXT_DIVP_2 0x01
#define DSU_CLK_REG_PLL_CPU1_OUT_EXT_DIVP_4 0x10

#define AHB_CLK_REG 0x00000510//AHB Clock Register
#define AHB_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define AHB_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x03000000
#define AHB_CLK_REG_CLK_SRC_SEL_HOSC 0x00
#define AHB_CLK_REG_CLK_SRC_SEL_CLK32K 0x01
#define AHB_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0x10
#define AHB_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS 0x11
#define AHB_CLK_REG_FACTOR_M_OFFSET 0
#define AHB_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define APB0_CLK_REG 0x00000520//APB0 Clock Register
#define APB0_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define APB0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x03000000
#define APB0_CLK_REG_CLK_SRC_SEL_HOSC 0x00
#define APB0_CLK_REG_CLK_SRC_SEL_CLK32K 0x01
#define APB0_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0x10
#define APB0_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS 0x11
#define APB0_CLK_REG_FACTOR_M_OFFSET 0
#define APB0_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define APB1_CLK_REG 0x00000524//APB1 Clock Register
#define APB1_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define APB1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x03000000
#define APB1_CLK_REG_CLK_SRC_SEL_HOSC 0x00
#define APB1_CLK_REG_CLK_SRC_SEL_CLK32K 0x01
#define APB1_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0x10
#define APB1_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS 0x11
#define APB1_CLK_REG_FACTOR_M_OFFSET 0
#define APB1_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define MBUS_CLK_REG 0x00000540//MBUS Clock Register
#define MBUS_CLK_REG_SCLK_GATING_OFFSET 31
#define MBUS_CLK_REG_SCLK_GATING_CLEAR_MASK 0x80000000
#define MBUS_CLK_REG_SCLK_GATING_CLOCK_IS_OFF 0x0
#define MBUS_CLK_REG_SCLK_GATING_CLOCK_IS_ON 0x1
#define MBUS_CLK_REG_MBUS_RST_OFFSET 30
#define MBUS_CLK_REG_MBUS_RST_CLEAR_MASK 0x40000000
#define MBUS_CLK_REG_MBUS_RST_ASSERT 0x0
#define MBUS_CLK_REG_MBUS_RST_DE_ASSERT 0x1
#define MBUS_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define MBUS_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define MBUS_CLK_REG_CLK_SRC_SEL_HOSC 0x000
#define MBUS_CLK_REG_CLK_SRC_SEL_DDRPLL 0x001
#define MBUS_CLK_REG_CLK_SRC_SEL_PERI0_600M 0x010
#define MBUS_CLK_REG_CLK_SRC_SEL_PERI0_480M 0x011
#define MBUS_CLK_REG_CLK_SRC_SEL_PERI0_400M 0x100
#define MBUS_CLK_REG_FACTOR_M_OFFSET 0
#define MBUS_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define NSI_BGR_REG 0x0000054c//NSI Bus Gating Reset Register
#define NSI_BGR_REG_NSI_RST_OFFSET 16
#define NSI_BGR_REG_NSI_RST_CLEAR_MASK 0x00010000
#define NSI_BGR_REG_NSI_RST_ASSERT 0x0
#define NSI_BGR_REG_NSI_RST_DE_ASSERT 0x1
#define NSI_BGR_REG_NSI_GATING_OFFSET 0
#define NSI_BGR_REG_NSI_GATING_CLEAR_MASK 0x00000001
#define NSI_BGR_REG_NSI_GATING_MASK 0x0
#define NSI_BGR_REG_NSI_GATING_PASS 0x1

#define GIC_CLK_REG 0x00000550//GIC Clock Register
#define GIC_CLK_REG_GIC_CLK_GATING_OFFSET 31
#define GIC_CLK_REG_GIC_CLK_GATING_CLEAR_MASK 0x80000000
#define GIC_CLK_REG_GIC_CLK_GATING_CLOCK_IS_OFF 0x0
#define GIC_CLK_REG_GIC_CLK_GATING_CLOCK_IS_ON 0x1
#define GIC_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define GIC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x03000000
#define GIC_CLK_REG_CLK_SRC_SEL_HOSC 0x000
#define GIC_CLK_REG_CLK_SRC_SEL_CLK32K 0x001
#define GIC_CLK_REG_CLK_SRC_SEL_PERI0_600M 0x010
#define GIC_CLK_REG_CLK_SRC_SEL_PERI0_480M 0x011
#define GIC_CLK_REG_FACTOR_M_OFFSET 0
#define GIC_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define DE0_CLK_REG 0x00000600//DE0 Clock Register
#define DE0_CLK_REG_DE_CLK_GATING_OFFSET 31
#define DE0_CLK_REG_DE_CLK_GATING_CLEAR_MASK 0x80000000
#define DE0_CLK_REG_DE_CLK_GATING_CLOCK_IS_OFF 0x0
#define DE0_CLK_REG_DE_CLK_GATING_CLOCK_IS_ON 0x1
#define DE0_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define DE0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define DE0_CLK_REG_CLK_SRC_SEL_PERI0_300M 0x000
#define DE0_CLK_REG_CLK_SRC_SEL_PERI0_400M 0x001
#define DE0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0x010
#define DE0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0x011
#define DE0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X 0x100
#define DE0_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X 0x101
#define DE0_CLK_REG_FACTOR_M_OFFSET 0
#define DE0_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define DE_BGR_REG 0x0000060c//DE Bus Gating Reset Register
#define DE_BGR_REG_DE0_RST_OFFSET 16
#define DE_BGR_REG_DE0_RST_CLEAR_MASK 0x00010000
#define DE_BGR_REG_DE0_RST_ASSERT 0x0
#define DE_BGR_REG_DE0_RST_DE_ASSERT 0x1
#define DE_BGR_REG_DE0_GATING_OFFSET 0
#define DE_BGR_REG_DE0_GATING_CLEAR_MASK 0x00000001
#define DE_BGR_REG_DE0_GATING_MASK 0x0
#define DE_BGR_REG_DE0_GATING_PASS 0x1

#define DI_CLK_REG 0x00000620//DI Clock Register
#define DI_CLK_REG_DI_CLK_GATING_OFFSET 31
#define DI_CLK_REG_DI_CLK_GATING_CLEAR_MASK 0x80000000
#define DI_CLK_REG_DI_CLK_GATING_CLOCK_IS_OFF 0x0
#define DI_CLK_REG_DI_CLK_GATING_CLOCK_IS_ON 0x1
#define DI_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define DI_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define DI_CLK_REG_CLK_SRC_SEL_PERI0_400M 0x000
#define DI_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0x010
#define DI_CLK_REG_FACTOR_M_OFFSET 0
#define DI_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define DI_BGR_REG 0x0000062c//DI Bus Gating Reset Register
#define DI_BGR_REG_DI_RST_OFFSET 16
#define DI_BGR_REG_DI_RST_CLEAR_MASK 0x00010000
#define DI_BGR_REG_DI_RST_ASSERT 0x0
#define DI_BGR_REG_DI_RST_DE_ASSERT 0x1
#define DI_BGR_REG_DI_GATING_OFFSET 0
#define DI_BGR_REG_DI_GATING_CLEAR_MASK 0x00000001
#define DI_BGR_REG_DI_GATING_MASK 0x0
#define DI_BGR_REG_DI_GATING_PASS 0x1

#define G2D_CLK_REG 0x00000630//G2D Clock Register
#define G2D_CLK_REG_G2D_CLK_GATING_OFFSET 31
#define G2D_CLK_REG_G2D_CLK_GATING_CLEAR_MASK 0x80000000
#define G2D_CLK_REG_G2D_CLK_GATING_CLOCK_IS_OFF 0x0
#define G2D_CLK_REG_G2D_CLK_GATING_CLOCK_IS_ON 0x1
#define G2D_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define G2D_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define G2D_CLK_REG_CLK_SRC_SEL_PERI0_400M 0x000
#define G2D_CLK_REG_CLK_SRC_SEL_PERI0_300M 0x001
#define G2D_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0x010
#define G2D_CLK_REG_FACTOR_M_OFFSET 0
#define G2D_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define G2D_BGR_REG 0x0000063c//G2D Bus Gating Reset Register
#define G2D_BGR_REG_G2D_RST_OFFSET 16
#define G2D_BGR_REG_G2D_RST_CLEAR_MASK 0x00010000
#define G2D_BGR_REG_G2D_RST_ASSERT 0x0
#define G2D_BGR_REG_G2D_RST_DE_ASSERT 0x1
#define G2D_BGR_REG_G2D_GATING_OFFSET 0
#define G2D_BGR_REG_G2D_GATING_CLEAR_MASK 0x00000001
#define G2D_BGR_REG_G2D_GATING_MASK 0x0
#define G2D_BGR_REG_G2D_GATING_PASS 0x1

#define GPU_CORE_CLK_REG 0x00000670//GPU_CORE Clock Register
#define GPU_CORE_CLK_REG_GPU_CORE_CLK_GATING_OFFSET 31
#define GPU_CORE_CLK_REG_GPU_CORE_CLK_GATING_CLEAR_MASK 0x80000000
#define GPU_CORE_CLK_REG_GPU_CORE_CLK_GATING_CLOCK_IS_OFF 0x0
#define GPU_CORE_CLK_REG_GPU_CORE_CLK_GATING_CLOCK_IS_ON 0x1
#define GPU_CORE_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define GPU_CORE_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define GPU_CORE_CLK_REG_CLK_SRC_SEL_GPUPLL 0x000
#define GPU_CORE_CLK_REG_CLK_SRC_SEL_PERI0_800M 0x001
#define GPU_CORE_CLK_REG_CLK_SRC_SEL_PERI0_600M 0x010
#define GPU_CORE_CLK_REG_CLK_SRC_SEL_PERI0_400M 0x011
#define GPU_CORE_CLK_REG_CLK_SRC_SEL_PERI0_300M 0x100
#define GPU_CORE_CLK_REG_CLK_SRC_SEL_PERI0_200M 0x101
#define GPU_CORE_CLK_REG_FACTOR_M_OFFSET 0
#define GPU_CORE_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000000f
#define GPU_CORE_CLK_REG_FACTOR_M_NOT_MASK 0x000
#define GPU_CORE_CLK_REG_FACTOR_M_MASK_1_CYCLE_AT_16_CYCLES 0x001
#define GPU_CORE_CLK_REG_FACTOR_M_MASK_2_CYCLES_AT_16_CYCLES 0x010

#define GPU_GATING_REG 0x0000067c//GPU Gating Reset Configuration Register
#define GPU_GATING_REG_GPU_RST_OFFSET 16
#define GPU_GATING_REG_GPU_RST_CLEAR_MASK 0x00010000
#define GPU_GATING_REG_GPU_RST_ASSERT 0x0
#define GPU_GATING_REG_GPU_RST_DE_ASSERT 0x1
#define GPU_GATING_REG_GPU_GATING_OFFSET 0
#define GPU_GATING_REG_GPU_GATING_CLEAR_MASK 0x00000001
#define GPU_GATING_REG_GPU_GATING_MASK 0x0
#define GPU_GATING_REG_GPU_GATING_PASS 0x1

#define CE_CLK_REG 0x00000680//CE Clock Register
#define CE_CLK_REG_CE_CLK_GATING_OFFSET 31
#define CE_CLK_REG_CE_CLK_GATING_CLEAR_MASK 0x80000000
#define CE_CLK_REG_CE_CLK_GATING_CLOCK_IS_OFF 0x0
#define CE_CLK_REG_CE_CLK_GATING_CLOCK_IS_ON 0x1
#define CE_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define CE_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define CE_CLK_REG_CLK_SRC_SEL_HOSC 0b0
#define CE_CLK_REG_CLK_SRC_SEL_PERI0_480M 0b1
#define CE_CLK_REG_CLK_SRC_SEL_PERI0_400M 0b10
#define CE_CLK_REG_CLK_SRC_SEL_PERI0_300M 0b11
#define CE_CLK_REG_FACTOR_M_OFFSET 0
#define CE_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define CE_BGR_REG 0x0000068c//CE Bus Gating Reset Register
#define CE_BGR_REG_CE_SYS_RST_OFFSET 17
#define CE_BGR_REG_CE_SYS_RST_CLEAR_MASK 0x00020000
#define CE_BGR_REG_CE_SYS_RST_ASSERT 0x0
#define CE_BGR_REG_CE_SYS_RST_DE_ASSERT 0x1
#define CE_BGR_REG_CE_RST_OFFSET 16
#define CE_BGR_REG_CE_RST_CLEAR_MASK 0x00010000
#define CE_BGR_REG_CE_RST_ASSERT 0x0
#define CE_BGR_REG_CE_RST_DE_ASSERT 0x1
#define CE_BGR_REG_CE_SYS_GATING_OFFSET 1
#define CE_BGR_REG_CE_SYS_GATING_CLEAR_MASK 0x00000002
#define CE_BGR_REG_CE_SYS_GATING_MASK 0x0
#define CE_BGR_REG_CE_SYS_GATING_PASS 0x1
#define CE_BGR_REG_CE_GATING_OFFSET 0
#define CE_BGR_REG_CE_GATING_CLEAR_MASK 0x00000001
#define CE_BGR_REG_CE_GATING_MASK 0x0
#define CE_BGR_REG_CE_GATING_PASS 0x1

#define VE_CLK_REG 0x00000690//VE Clock Register
#define VE_CLK_REG_VE_CLK_GATING_OFFSET 31
#define VE_CLK_REG_VE_CLK_GATING_CLEAR_MASK 0x80000000
#define VE_CLK_REG_VE_CLK_GATING_CLOCK_IS_OFF 0x0
#define VE_CLK_REG_VE_CLK_GATING_CLOCK_IS_ON 0x1
#define VE_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define VE_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define VE_CLK_REG_CLK_SRC_SEL_VEPLL 0x000
#define VE_CLK_REG_CLK_SRC_SEL_PERI0_480M 0x001
#define VE_CLK_REG_CLK_SRC_SEL_PERI0_400M 0x010
#define VE_CLK_REG_CLK_SRC_SEL_PERI0_300M 0x011
#define VE_CLK_REG_FACTOR_M_OFFSET 0
#define VE_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define VE_BGR_REG 0x0000069c//VE Bus Gating Reset Register
#define VE_BGR_REG_VE_RST_OFFSET 16
#define VE_BGR_REG_VE_RST_CLEAR_MASK 0x00010000
#define VE_BGR_REG_VE_RST_ASSERT 0x0
#define VE_BGR_REG_VE_RST_DE_ASSERT 0x1
#define VE_BGR_REG_VE_GATING_OFFSET 0
#define VE_BGR_REG_VE_GATING_CLEAR_MASK 0x00000001
#define VE_BGR_REG_VE_GATING_MASK 0x0
#define VE_BGR_REG_VE_GATING_PASS 0x1

#define NPU_CLK_REG 0x000006e0//NPU Clock Register
#define NPU_CLK_REG_NPU_CLK_GATING_OFFSET 31
#define NPU_CLK_REG_NPU_CLK_GATING_CLEAR_MASK 0x80000000
#define NPU_CLK_REG_NPU_CLK_GATING_CLOCK_IS_OFF 0x0
#define NPU_CLK_REG_NPU_CLK_GATING_CLOCK_IS_ON 0x1
#define NPU_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define NPU_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define NPU_CLK_REG_CLK_SRC_SEL_PERI0_480M 0x000
#define NPU_CLK_REG_CLK_SRC_SEL_PERI0_600M 0x001
#define NPU_CLK_REG_CLK_SRC_SEL_PERI0_800M 0x010
#define NPU_CLK_REG_CLK_SRC_SEL_NPUPLL4X 0x011
#define NPU_CLK_REG_FACTOR_M_OFFSET 0
#define NPU_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define DMA_BGR_REG 0x0000070c//DMA Bus Gating Reset Register
#define DMA_BGR_REG_DMA_RST_OFFSET 16
#define DMA_BGR_REG_DMA_RST_CLEAR_MASK 0x00010000
#define DMA_BGR_REG_DMA_RST_ASSERT 0x0
#define DMA_BGR_REG_DMA_RST_DE_ASSERT 0x1
#define DMA_BGR_REG_DMA_GATING_OFFSET 0
#define DMA_BGR_REG_DMA_GATING_CLEAR_MASK 0x00000001
#define DMA_BGR_REG_DMA_GATING_MASK 0x0
#define DMA_BGR_REG_DMA_GATING_PASS 0x1

#define MSGBOX_BGR_REG 0x0000071c//MSGBOX Bus Gating Reset Register
#define MSGBOX_BGR_REG_MSGBOX1_RST_OFFSET 17
#define MSGBOX_BGR_REG_MSGBOX1_RST_CLEAR_MASK 0x00020000
#define MSGBOX_BGR_REG_MSGBOX1_RST_ASSERT 0x0
#define MSGBOX_BGR_REG_MSGBOX1_RST_DE_ASSERT 0x1
#define MSGBOX_BGR_REG_MSGBOX0_RST_OFFSET 16
#define MSGBOX_BGR_REG_MSGBOX0_RST_CLEAR_MASK 0x00010000
#define MSGBOX_BGR_REG_MSGBOX0_RST_ASSERT 0x0
#define MSGBOX_BGR_REG_MSGBOX0_RST_DE_ASSERT 0x1
#define MSGBOX_BGR_REG_MSGBOX1_GATING_OFFSET 1
#define MSGBOX_BGR_REG_MSGBOX1_GATING_CLEAR_MASK 0x00000002
#define MSGBOX_BGR_REG_MSGBOX1_GATING_MASK 0x0
#define MSGBOX_BGR_REG_MSGBOX1_GATING_PASS 0x1
#define MSGBOX_BGR_REG_MSGBOX0_GATING_OFFSET 0
#define MSGBOX_BGR_REG_MSGBOX0_GATING_CLEAR_MASK 0x00000001
#define MSGBOX_BGR_REG_MSGBOX0_GATING_MASK 0x0
#define MSGBOX_BGR_REG_MSGBOX0_GATING_PASS 0x1

#define SPINLOCK_BGR_REG 0x0000072c//SPINLOCK Bus Gating Reset Register
#define SPINLOCK_BGR_REG_SPINLOCK_RST_OFFSET 16
#define SPINLOCK_BGR_REG_SPINLOCK_RST_CLEAR_MASK 0x00010000
#define SPINLOCK_BGR_REG_SPINLOCK_RST_ASSERT 0x0
#define SPINLOCK_BGR_REG_SPINLOCK_RST_DE_ASSERT 0x1
#define SPINLOCK_BGR_REG_SPINLOCK_GATING_OFFSET 0
#define SPINLOCK_BGR_REG_SPINLOCK_GATING_CLEAR_MASK 0x00000001
#define SPINLOCK_BGR_REG_SPINLOCK_GATING_MASK 0x0
#define SPINLOCK_BGR_REG_SPINLOCK_GATING_PASS 0x1

#define TIMER0_CLK_REG 0x00000730//TIMER0 Clock Register
#define TIMER0_CLK_REG_TIMER0_CLK_GATING_OFFSET 31
#define TIMER0_CLK_REG_TIMER0_CLK_GATING_CLEAR_MASK 0x80000000
#define TIMER0_CLK_REG_TIMER0_CLK_GATING_DISABLE 0x0
#define TIMER0_CLK_REG_TIMER0_CLK_GATING_ENABLE 0x1
#define TIMER0_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define TIMER0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define TIMER0_CLK_REG_CLK_SRC_SEL_HOSC 0x000
#define TIMER0_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0x001
#define TIMER0_CLK_REG_CLK_SRC_SEL_CLK32K 0x010
#define TIMER0_CLK_REG_CLK_SRC_SEL_PERI0_200M 0x011
#define TIMER0_CLK_REG_FACTOR_M_OFFSET 0
#define TIMER0_CLK_REG_FACTOR_M_CLEAR_MASK 0x00000007
#define TIMER0_CLK_REG_FACTOR_M__1 0x000
#define TIMER0_CLK_REG_FACTOR_M__2 0x001
#define TIMER0_CLK_REG_FACTOR_M__4 0x010
#define TIMER0_CLK_REG_FACTOR_M__8 0x011
#define TIMER0_CLK_REG_FACTOR_M__16 0x100
#define TIMER0_CLK_REG_FACTOR_M__32 0x101
#define TIMER0_CLK_REG_FACTOR_M__64 0x110
#define TIMER0_CLK_REG_FACTOR_M__128 0x111

#define TIMER1_CLK_REG 0x00000734//TIMER1 Clock Register
#define TIMER1_CLK_REG_TIMER1_CLK_GATING_OFFSET 31
#define TIMER1_CLK_REG_TIMER1_CLK_GATING_CLEAR_MASK 0x80000000
#define TIMER1_CLK_REG_TIMER1_CLK_GATING_DISABLE 0x0
#define TIMER1_CLK_REG_TIMER1_CLK_GATING_ENABLE 0x1
#define TIMER1_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define TIMER1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define TIMER1_CLK_REG_CLK_SRC_SEL_HOSC 0x000
#define TIMER1_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0x001
#define TIMER1_CLK_REG_CLK_SRC_SEL_CLK32K 0x010
#define TIMER1_CLK_REG_CLK_SRC_SEL_PERI0_200M 0x011
#define TIMER1_CLK_REG_FACTOR_M_OFFSET 0
#define TIMER1_CLK_REG_FACTOR_M_CLEAR_MASK 0x00000007
#define TIMER1_CLK_REG_FACTOR_M__1 0x000
#define TIMER1_CLK_REG_FACTOR_M__2 0x001
#define TIMER1_CLK_REG_FACTOR_M__4 0x010
#define TIMER1_CLK_REG_FACTOR_M__8 0x011
#define TIMER1_CLK_REG_FACTOR_M__16 0x100
#define TIMER1_CLK_REG_FACTOR_M__32 0x101
#define TIMER1_CLK_REG_FACTOR_M__64 0x110
#define TIMER1_CLK_REG_FACTOR_M__128 0x111

#define TIMER2_CLK_REG 0x00000738//TIMER2 Clock Register
#define TIMER2_CLK_REG_TIMER2_CLK_GATING_OFFSET 31
#define TIMER2_CLK_REG_TIMER2_CLK_GATING_CLEAR_MASK 0x80000000
#define TIMER2_CLK_REG_TIMER2_CLK_GATING_DISABLE 0x0
#define TIMER2_CLK_REG_TIMER2_CLK_GATING_ENABLE 0x1
#define TIMER2_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define TIMER2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define TIMER2_CLK_REG_CLK_SRC_SEL_HOSC 0x00
#define TIMER2_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0x001
#define TIMER2_CLK_REG_CLK_SRC_SEL_CLK32K 0x010
#define TIMER2_CLK_REG_CLK_SRC_SEL_PERI0_200M 0x011
#define TIMER2_CLK_REG_FACTOR_M_OFFSET 0
#define TIMER2_CLK_REG_FACTOR_M_CLEAR_MASK 0x00000007
#define TIMER2_CLK_REG_FACTOR_M__1 0x000
#define TIMER2_CLK_REG_FACTOR_M__2 0x001
#define TIMER2_CLK_REG_FACTOR_M__4 0x010
#define TIMER2_CLK_REG_FACTOR_M__8 0x011
#define TIMER2_CLK_REG_FACTOR_M__16 0x100
#define TIMER2_CLK_REG_FACTOR_M__32 0x101
#define TIMER2_CLK_REG_FACTOR_M__64 0x110
#define TIMER2_CLK_REG_FACTOR_M__128 0x111

#define TIMER3_CLK_REG 0x0000073c//TIMER3 Clock Register
#define TIMER3_CLK_REG_TIMER3_CLK_GATING_OFFSET 31
#define TIMER3_CLK_REG_TIMER3_CLK_GATING_CLEAR_MASK 0x80000000
#define TIMER3_CLK_REG_TIMER3_CLK_GATING_DISABLE 0x0
#define TIMER3_CLK_REG_TIMER3_CLK_GATING_ENABLE 0x1
#define TIMER3_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define TIMER3_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define TIMER3_CLK_REG_CLK_SRC_SEL_HOSC 0x000
#define TIMER3_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0x001
#define TIMER3_CLK_REG_CLK_SRC_SEL_CLK32K 0x010
#define TIMER3_CLK_REG_CLK_SRC_SEL_PERI0_200M 0x011
#define TIMER3_CLK_REG_FACTOR_M_OFFSET 0
#define TIMER3_CLK_REG_FACTOR_M_CLEAR_MASK 0x00000007
#define TIMER3_CLK_REG_FACTOR_M__1 0x000
#define TIMER3_CLK_REG_FACTOR_M__2 0x001
#define TIMER3_CLK_REG_FACTOR_M__4 0x010
#define TIMER3_CLK_REG_FACTOR_M__8 0x011
#define TIMER3_CLK_REG_FACTOR_M__16 0x100
#define TIMER3_CLK_REG_FACTOR_M__32 0x101
#define TIMER3_CLK_REG_FACTOR_M__64 0x110
#define TIMER3_CLK_REG_FACTOR_M__128 0x111

#define TIMER4_CLK_REG 0x00000740//TIMER4 Clock Register
#define TIMER4_CLK_REG_TIMER4_CLK_GATING_OFFSET 31
#define TIMER4_CLK_REG_TIMER4_CLK_GATING_CLEAR_MASK 0x80000000
#define TIMER4_CLK_REG_TIMER4_CLK_GATING_DISABLE 0x0
#define TIMER4_CLK_REG_TIMER4_CLK_GATING_ENABLE 0x1
#define TIMER4_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define TIMER4_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define TIMER4_CLK_REG_CLK_SRC_SEL_HOSC 0x000
#define TIMER4_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0x001
#define TIMER4_CLK_REG_CLK_SRC_SEL_CLK32K 0x010
#define TIMER4_CLK_REG_CLK_SRC_SEL_PERI0_200M 0x011
#define TIMER4_CLK_REG_FACTOR_M_OFFSET 0
#define TIMER4_CLK_REG_FACTOR_M_CLEAR_MASK 0x00000007
#define TIMER4_CLK_REG_FACTOR_M__1 0x000
#define TIMER4_CLK_REG_FACTOR_M__2 0x001
#define TIMER4_CLK_REG_FACTOR_M__4 0x010
#define TIMER4_CLK_REG_FACTOR_M__8 0x011
#define TIMER4_CLK_REG_FACTOR_M__16 0x100
#define TIMER4_CLK_REG_FACTOR_M__32 0x101
#define TIMER4_CLK_REG_FACTOR_M__64 0x110
#define TIMER4_CLK_REG_FACTOR_M__128 0x111

#define TIMER5_CLK_REG 0x00000744//TIMER5 Clock Register
#define TIMER5_CLK_REG_TIMER5_CLK_GATING_OFFSET 31
#define TIMER5_CLK_REG_TIMER5_CLK_GATING_CLEAR_MASK 0x80000000
#define TIMER5_CLK_REG_TIMER5_CLK_GATING_DISABLE 0x0
#define TIMER5_CLK_REG_TIMER5_CLK_GATING_ENABLE 0x1
#define TIMER5_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define TIMER5_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define TIMER5_CLK_REG_CLK_SRC_SEL_HOSC 0x000
#define TIMER5_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0x001
#define TIMER5_CLK_REG_CLK_SRC_SEL_CLK32K 0x010
#define TIMER5_CLK_REG_CLK_SRC_SEL_PERI0_200M 0x011
#define TIMER5_CLK_REG_FACTOR_M_OFFSET 0
#define TIMER5_CLK_REG_FACTOR_M_CLEAR_MASK 0x00000007
#define TIMER5_CLK_REG_FACTOR_M__1 0x000
#define TIMER5_CLK_REG_FACTOR_M__2 0x001
#define TIMER5_CLK_REG_FACTOR_M__4 0x010
#define TIMER5_CLK_REG_FACTOR_M__8 0x011
#define TIMER5_CLK_REG_FACTOR_M__16 0x100
#define TIMER5_CLK_REG_FACTOR_M__32 0x101
#define TIMER5_CLK_REG_FACTOR_M__64 0x110
#define TIMER5_CLK_REG_FACTOR_M__128 0x111

#define TIMER_BGR_REG 0x0000074c//TIMER Bus Gating Reset Register
#define TIMER_BGR_REG_TIMER_RST_OFFSET 16
#define TIMER_BGR_REG_TIMER_RST_CLEAR_MASK 0x00010000
#define TIMER_BGR_REG_TIMER_RST_ASSERT 0x0
#define TIMER_BGR_REG_TIMER_RST_DE_ASSERT 0x1
#define TIMER_BGR_REG_TIMER_GATING_OFFSET 0
#define TIMER_BGR_REG_TIMER_GATING_CLEAR_MASK 0x00000001
#define TIMER_BGR_REG_TIMER_GATING_MASK 0x0
#define TIMER_BGR_REG_TIMER_GATING_PASS 0x1

#define AVS_CLK_REG 0x00000750//AVS Clock Register
#define AVS_CLK_REG_AVS_CLK_GATING_OFFSET 31
#define AVS_CLK_REG_AVS_CLK_GATING_CLEAR_MASK 0x80000000
#define AVS_CLK_REG_AVS_CLK_GATING_CLOCK_IS_OFF 0x0
#define AVS_CLK_REG_AVS_CLK_GATING_CLOCK_IS_ON 0x1

#define DBGSYS_BGR_REG 0x0000078c//DBGSYS Bus Gating Reset Register
#define DBGSYS_BGR_REG_DBGSYS_RST_OFFSET 16
#define DBGSYS_BGR_REG_DBGSYS_RST_CLEAR_MASK 0x00010000
#define DBGSYS_BGR_REG_DBGSYS_RST_ASSERT 0x0
#define DBGSYS_BGR_REG_DBGSYS_RST_DE_ASSERT 0x1
#define DBGSYS_BGR_REG_DBGSYS_GATING_OFFSET 0
#define DBGSYS_BGR_REG_DBGSYS_GATING_CLEAR_MASK 0x00000001
#define DBGSYS_BGR_REG_DBGSYS_GATING_MASK 0x0
#define DBGSYS_BGR_REG_DBGSYS_GATING_PASS 0x1

#define PWM_BGR_REG 0x000007ac//PWM Bus Gating Reset Register
#define PWM_BGR_REG_PWM_RST_OFFSET 16
#define PWM_BGR_REG_PWM_RST_CLEAR_MASK 0x00010000
#define PWM_BGR_REG_PWM_RST_ASSERT 0x0
#define PWM_BGR_REG_PWM_RST_DE_ASSERT 0x1
#define PWM_BGR_REG_PWM_GATING_OFFSET 0
#define PWM_BGR_REG_PWM_GATING_CLEAR_MASK 0x00000001
#define PWM_BGR_REG_PWM_GATING_MASK 0x0
#define PWM_BGR_REG_PWM_GATING_PASS 0x1

#define IOMMU_BGR_REG 0x000007bc//IOMMU Bus Gating Reset Register
#define IOMMU_BGR_REG_IOMMU_GATING_OFFSET 0
#define IOMMU_BGR_REG_IOMMU_GATING_CLEAR_MASK 0x00000001
#define IOMMU_BGR_REG_IOMMU_GATING_MASK 0x0
#define IOMMU_BGR_REG_IOMMU_GATING_PASS 0x1

#define DRAM_CLK_REG 0x00000800//DRAM Clock Register
#define DRAM_CLK_REG_DRAM_CLK_GATING_OFFSET 31
#define DRAM_CLK_REG_DRAM_CLK_GATING_CLEAR_MASK 0x80000000
#define DRAM_CLK_REG_DRAM_CLK_GATING_CLOCK_IS_OFF 0x0
#define DRAM_CLK_REG_DRAM_CLK_GATING_CLOCK_IS_ON 0x1
#define DRAM_CLK_REG_DRAM_UPD_OFFSET 27
#define DRAM_CLK_REG_DRAM_UPD_CLEAR_MASK 0x08000000
#define DRAM_CLK_REG_DRAM_UPD_INVALID 0x0
#define DRAM_CLK_REG_DRAM_UPD_VALID 0x1
#define DRAM_CLK_REG_DRAM_CLK_SEL_OFFSET 24
#define DRAM_CLK_REG_DRAM_CLK_SEL_CLEAR_MASK 0x07000000
#define DRAM_CLK_REG_DRAM_CLK_SEL_DDRPLL 0x000
#define DRAM_CLK_REG_DRAM_CLK_SEL_PERI1_600M 0x001
#define DRAM_CLK_REG_DRAM_CLK_SEL_PERI1_480M 0x010
#define DRAM_CLK_REG_DRAM_CLK_SEL_PERI1_400M 0x011
#define DRAM_CLK_REG_DRAM_CLK_SEL_PERI1_150M 0x100
#define DRAM_CLK_REG_DRAM_DIV1_OFFSET 0
#define DRAM_CLK_REG_DRAM_DIV1_CLEAR_MASK 0x0000001f

#define MBUS_MAT_CLK_GATING_REG 0x00000804//MBUS Master Clock Gating Register
#define MBUS_MAT_CLK_GATING_REG_NAND_MBUS_GATE_SW_CFG_OFFSET 22
#define MBUS_MAT_CLK_GATING_REG_NAND_MBUS_GATE_SW_CFG_CLEAR_MASK 0x00400000
#define MBUS_MAT_CLK_GATING_REG_NAND_MBUS_GATE_SW_CFG_DISABLE 0x0
#define MBUS_MAT_CLK_GATING_REG_NAND_MBUS_GATE_SW_CFG_ENABLE 0x1
#define MBUS_MAT_CLK_GATING_REG_NPU_MBUS_GATE_SW_CFG_OFFSET 21
#define MBUS_MAT_CLK_GATING_REG_NPU_MBUS_GATE_SW_CFG_CLEAR_MASK 0x00200000
#define MBUS_MAT_CLK_GATING_REG_NPU_MBUS_GATE_SW_CFG_DISABLE 0x0
#define MBUS_MAT_CLK_GATING_REG_NPU_MBUS_GATE_SW_CFG_ENABLE 0x1
#define MBUS_MAT_CLK_GATING_REG_VID_IN_MBUS_GATE_SW_CFG_OFFSET 20
#define MBUS_MAT_CLK_GATING_REG_VID_IN_MBUS_GATE_SW_CFG_CLEAR_MASK 0x00100000
#define MBUS_MAT_CLK_GATING_REG_VID_IN_MBUS_GATE_SW_CFG_DISABLE 0x0
#define MBUS_MAT_CLK_GATING_REG_VID_IN_MBUS_GATE_SW_CFG_ENABLE 0x1
#define MBUS_MAT_CLK_GATING_REG_VID_OUT_MBUS_GATE_SW_CFG_OFFSET 19
#define MBUS_MAT_CLK_GATING_REG_VID_OUT_MBUS_GATE_SW_CFG_CLEAR_MASK 0x00080000
#define MBUS_MAT_CLK_GATING_REG_VID_OUT_MBUS_GATE_SW_CFG_DISABLE 0x0
#define MBUS_MAT_CLK_GATING_REG_VID_OUT_MBUS_GATE_SW_CFG_ENABLE 0x1
#define MBUS_MAT_CLK_GATING_REG_CE_MBUS_GATE_SW_CFG_OFFSET 18
#define MBUS_MAT_CLK_GATING_REG_CE_MBUS_GATE_SW_CFG_CLEAR_MASK 0x00040000
#define MBUS_MAT_CLK_GATING_REG_CE_MBUS_GATE_SW_CFG_DISABLE 0x0
#define MBUS_MAT_CLK_GATING_REG_CE_MBUS_GATE_SW_CFG_ENABLE 0x1
#define MBUS_MAT_CLK_GATING_REG_VE_MBUS_GATE_SW_CFG_OFFSET 17
#define MBUS_MAT_CLK_GATING_REG_VE_MBUS_GATE_SW_CFG_CLEAR_MASK 0x00020000
#define MBUS_MAT_CLK_GATING_REG_VE_MBUS_GATE_SW_CFG_DISABLE 0x0
#define MBUS_MAT_CLK_GATING_REG_VE_MBUS_GATE_SW_CFG_ENABLE 0x1
#define MBUS_MAT_CLK_GATING_REG_DMA_MBUS_GATE_SW_CFG_OFFSET 16
#define MBUS_MAT_CLK_GATING_REG_DMA_MBUS_GATE_SW_CFG_CLEAR_MASK 0x00010000
#define MBUS_MAT_CLK_GATING_REG_DMA_MBUS_GATE_SW_CFG_DISABLE 0x0
#define MBUS_MAT_CLK_GATING_REG_DMA_MBUS_GATE_SW_CFG_ENABLE 0x1
#define MBUS_MAT_CLK_GATING_REG_ISP_MCLK_EN_OFFSET 9
#define MBUS_MAT_CLK_GATING_REG_ISP_MCLK_EN_CLEAR_MASK 0x00000200
#define MBUS_MAT_CLK_GATING_REG_ISP_MCLK_EN_MASK 0x0
#define MBUS_MAT_CLK_GATING_REG_ISP_MCLK_EN_PASS 0x1
#define MBUS_MAT_CLK_GATING_REG_CSI_MCLK_EN_OFFSET 8
#define MBUS_MAT_CLK_GATING_REG_CSI_MCLK_EN_CLEAR_MASK 0x00000100
#define MBUS_MAT_CLK_GATING_REG_CSI_MCLK_EN_MASK 0x0
#define MBUS_MAT_CLK_GATING_REG_CSI_MCLK_EN_PASS 0x1
#define MBUS_MAT_CLK_GATING_REG_USB3_MCLK_EN_OFFSET 6
#define MBUS_MAT_CLK_GATING_REG_USB3_MCLK_EN_CLEAR_MASK 0x00000040
#define MBUS_MAT_CLK_GATING_REG_USB3_MCLK_EN_MASK 0x0
#define MBUS_MAT_CLK_GATING_REG_USB3_MCLK_EN_PASS 0x1
#define MBUS_MAT_CLK_GATING_REG_NAND_MCLK_EN_OFFSET 5
#define MBUS_MAT_CLK_GATING_REG_NAND_MCLK_EN_CLEAR_MASK 0x00000020
#define MBUS_MAT_CLK_GATING_REG_NAND_MCLK_EN_MASK 0x0
#define MBUS_MAT_CLK_GATING_REG_NAND_MCLK_EN_PASS 0x1
#define MBUS_MAT_CLK_GATING_REG_CE_MCLK_EN_OFFSET 2
#define MBUS_MAT_CLK_GATING_REG_CE_MCLK_EN_CLEAR_MASK 0x00000004
#define MBUS_MAT_CLK_GATING_REG_CE_MCLK_EN_MASK 0x0
#define MBUS_MAT_CLK_GATING_REG_CE_MCLK_EN_PASS 0x1
#define MBUS_MAT_CLK_GATING_REG_VE_MCLK_EN_OFFSET 1
#define MBUS_MAT_CLK_GATING_REG_VE_MCLK_EN_CLEAR_MASK 0x00000002
#define MBUS_MAT_CLK_GATING_REG_VE_MCLK_EN_MASK 0x0
#define MBUS_MAT_CLK_GATING_REG_VE_MCLK_EN_PASS 0x1
#define MBUS_MAT_CLK_GATING_REG_DMA_MCLK_EN_OFFSET 0
#define MBUS_MAT_CLK_GATING_REG_DMA_MCLK_EN_CLEAR_MASK 0x00000001
#define MBUS_MAT_CLK_GATING_REG_DMA_MCLK_EN_MASK 0x0
#define MBUS_MAT_CLK_GATING_REG_DMA_MCLK_EN_PASS 0x1

#define DRAM_BGR_REG 0x0000080c//DRAM Bus Gating Reset Register
#define DRAM_BGR_REG_DRAM_RST_OFFSET 16
#define DRAM_BGR_REG_DRAM_RST_CLEAR_MASK 0x00010000
#define DRAM_BGR_REG_DRAM_RST_ASSERT 0x0
#define DRAM_BGR_REG_DRAM_RST_DE_ASSERT 0x1
#define DRAM_BGR_REG_DRAM_GATING_OFFSET 0
#define DRAM_BGR_REG_DRAM_GATING_CLEAR_MASK 0x00000001
#define DRAM_BGR_REG_DRAM_GATING_MASK 0x0
#define DRAM_BGR_REG_DRAM_GATING_PASS 0x1

#define NAND0_CLK0_CLK_REG 0x00000810//NAND0 CLK0 Clock Register
#define NAND0_CLK0_CLK_REG_NAND0_CLK0_CLK_GATING_OFFSET 31
#define NAND0_CLK0_CLK_REG_NAND0_CLK0_CLK_GATING_CLEAR_MASK 0x80000000
#define NAND0_CLK0_CLK_REG_NAND0_CLK0_CLK_GATING_CLOCK_IS_OFF 0x0
#define NAND0_CLK0_CLK_REG_NAND0_CLK0_CLK_GATING_CLOCK_IS_ON 0x1
#define NAND0_CLK0_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define NAND0_CLK0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define NAND0_CLK0_CLK_REG_CLK_SRC_SEL_HOSC 0x000
#define NAND0_CLK0_CLK_REG_CLK_SRC_SEL_PERI0_400M 0x001
#define NAND0_CLK0_CLK_REG_CLK_SRC_SEL_PERI0_300M 0x010
#define NAND0_CLK0_CLK_REG_CLK_SRC_SEL_PERI1_400M 0x011
#define NAND0_CLK0_CLK_REG_CLK_SRC_SEL_PERI1_300M 0x100
#define NAND0_CLK0_CLK_REG_FACTOR_M_OFFSET 0
#define NAND0_CLK0_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define NAND0_CLK1_CLK_REG 0x00000814//NAND0 CLK1 Clock Register
#define NAND0_CLK1_CLK_REG_NAND0_CLK1_CLK_GATING_OFFSET 31
#define NAND0_CLK1_CLK_REG_NAND0_CLK1_CLK_GATING_CLEAR_MASK 0x80000000
#define NAND0_CLK1_CLK_REG_NAND0_CLK1_CLK_GATING_CLOCK_IS_OFF 0x0
#define NAND0_CLK1_CLK_REG_NAND0_CLK1_CLK_GATING_CLOCK_IS_ON 0x1
#define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_HOSC 0x000
#define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_PERI0_400M 0x001
#define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_PERI0_300M 0x010
#define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_PERI1_400M 0x011
#define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_PERI1_300M 0x100
#define NAND0_CLK1_CLK_REG_FACTOR_M_OFFSET 0
#define NAND0_CLK1_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define NAND_BGR_REG 0x0000082c//NAND Bus Gating Reset Register
#define NAND_BGR_REG_NAND0_RST_OFFSET 16
#define NAND_BGR_REG_NAND0_RST_CLEAR_MASK 0x00010000
#define NAND_BGR_REG_NAND0_RST_ASSERT 0x0
#define NAND_BGR_REG_NAND0_RST_DE_ASSERT 0x1
#define NAND_BGR_REG_NAND0_GATING_OFFSET 0
#define NAND_BGR_REG_NAND0_GATING_CLEAR_MASK 0x00000001
#define NAND_BGR_REG_NAND0_GATING_MASK 0x0
#define NAND_BGR_REG_NAND0_GATING_PASS 0x1

#define SMHC0_CLK_REG 0x00000830//SMHC0 Clock Register
#define SMHC0_CLK_REG_SMHC0_CLK_GATING_OFFSET 31
#define SMHC0_CLK_REG_SMHC0_CLK_GATING_CLEAR_MASK 0x80000000
#define SMHC0_CLK_REG_SMHC0_CLK_GATING_CLOCK_IS_OFF 0x0
#define SMHC0_CLK_REG_SMHC0_CLK_GATING_CLOCK_IS_ON 0x1
#define SMHC0_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define SMHC0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define SMHC0_CLK_REG_CLK_SRC_SEL_HOSC 0x000
#define SMHC0_CLK_REG_CLK_SRC_SEL_PERI0_400M 0x001
#define SMHC0_CLK_REG_CLK_SRC_SEL_PERI0_300M 0x010
#define SMHC0_CLK_REG_CLK_SRC_SEL_PERI1_400M 0x011
#define SMHC0_CLK_REG_CLK_SRC_SEL_PERI1_300M 0x100
#define SMHC0_CLK_REG_FACTOR_N_OFFSET 8
#define SMHC0_CLK_REG_FACTOR_N_CLEAR_MASK 0x00001f00
#define SMHC0_CLK_REG_FACTOR_M_OFFSET 0
#define SMHC0_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define SMHC1_CLK_REG 0x00000834//SMHC1 Clock Register
#define SMHC1_CLK_REG_SMHC1_CLK_GATING_OFFSET 31
#define SMHC1_CLK_REG_SMHC1_CLK_GATING_CLEAR_MASK 0x80000000
#define SMHC1_CLK_REG_SMHC1_CLK_GATING_CLOCK_IS_OFF 0x0
#define SMHC1_CLK_REG_SMHC1_CLK_GATING_CLOCK_IS_ON 0x1
#define SMHC1_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define SMHC1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define SMHC1_CLK_REG_CLK_SRC_SEL_HOSC 0x000
#define SMHC1_CLK_REG_CLK_SRC_SEL_PERI0_400M 0x001
#define SMHC1_CLK_REG_CLK_SRC_SEL_PERI0_300M 0x010
#define SMHC1_CLK_REG_CLK_SRC_SEL_PERI1_400M 0x011
#define SMHC1_CLK_REG_CLK_SRC_SEL_PERI1_300M 0x100
#define SMHC1_CLK_REG_FACTOR_N_OFFSET 8
#define SMHC1_CLK_REG_FACTOR_N_CLEAR_MASK 0x00001f00
#define SMHC1_CLK_REG_FACTOR_M_OFFSET 0
#define SMHC1_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define SMHC2_CLK_REG 0x00000838//SMHC2 Clock Register
#define SMHC2_CLK_REG_SMHC2_CLK_GATING_OFFSET 31
#define SMHC2_CLK_REG_SMHC2_CLK_GATING_CLEAR_MASK 0x80000000
#define SMHC2_CLK_REG_SMHC2_CLK_GATING_CLOCK_IS_OFF 0x0
#define SMHC2_CLK_REG_SMHC2_CLK_GATING_CLOCK_IS_ON 0x1
#define SMHC2_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define SMHC2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define SMHC2_CLK_REG_CLK_SRC_SEL_HOSC 0x000
#define SMHC2_CLK_REG_CLK_SRC_SEL_PERI0_800M 0x001
#define SMHC2_CLK_REG_CLK_SRC_SEL_PERI0_600M 0x010
#define SMHC2_CLK_REG_CLK_SRC_SEL_PERI1_800M 0x011
#define SMHC2_CLK_REG_CLK_SRC_SEL_PERI1_600M 0x100
#define SMHC2_CLK_REG_FACTOR_N_OFFSET 8
#define SMHC2_CLK_REG_FACTOR_N_CLEAR_MASK 0x00001f00
#define SMHC2_CLK_REG_FACTOR_M_OFFSET 0
#define SMHC2_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define SMHC_BGR_REG 0x0000084c//SMHC Bus Gating Reset Register
#define SMHC_BGR_REG_SMHC2_RST_OFFSET 18
#define SMHC_BGR_REG_SMHC2_RST_CLEAR_MASK 0x00040000
#define SMHC_BGR_REG_SMHC2_RST_ASSERT 0x0
#define SMHC_BGR_REG_SMHC2_RST_DE_ASSERT 0x1
#define SMHC_BGR_REG_SMHC1_RST_OFFSET 17
#define SMHC_BGR_REG_SMHC1_RST_CLEAR_MASK 0x00020000
#define SMHC_BGR_REG_SMHC1_RST_ASSERT 0x0
#define SMHC_BGR_REG_SMHC1_RST_DE_ASSERT 0x1
#define SMHC_BGR_REG_SMHC0_RST_OFFSET 16
#define SMHC_BGR_REG_SMHC0_RST_CLEAR_MASK 0x00010000
#define SMHC_BGR_REG_SMHC0_RST_ASSERT 0x0
#define SMHC_BGR_REG_SMHC0_RST_DE_ASSERT 0x1
#define SMHC_BGR_REG_SMHC2_GATING_OFFSET 2
#define SMHC_BGR_REG_SMHC2_GATING_CLEAR_MASK 0x00000004
#define SMHC_BGR_REG_SMHC2_GATING_MASK 0x0
#define SMHC_BGR_REG_SMHC2_GATING_PASS 0x1
#define SMHC_BGR_REG_SMHC1_GATING_OFFSET 1
#define SMHC_BGR_REG_SMHC1_GATING_CLEAR_MASK 0x00000002
#define SMHC_BGR_REG_SMHC1_GATING_MASK 0x0
#define SMHC_BGR_REG_SMHC1_GATING_PASS 0x1
#define SMHC_BGR_REG_SMHC0_GATING_OFFSET 0
#define SMHC_BGR_REG_SMHC0_GATING_CLEAR_MASK 0x00000001
#define SMHC_BGR_REG_SMHC0_GATING_MASK 0x0
#define SMHC_BGR_REG_SMHC0_GATING_PASS 0x1

#define SYSDAP_BGR_REG 0x0000088c//SYSDAP Bus Gating Reset Register
#define SYSDAP_BGR_REG_SYSDAP_RST_OFFSET 16
#define SYSDAP_BGR_REG_SYSDAP_RST_CLEAR_MASK 0x00010000
#define SYSDAP_BGR_REG_SYSDAP_RST_ASSERT 0x0
#define SYSDAP_BGR_REG_SYSDAP_RST_DE_ASSERT 0x1
#define SYSDAP_BGR_REG_SYSDAP_GATING_OFFSET 0
#define SYSDAP_BGR_REG_SYSDAP_GATING_CLEAR_MASK 0x00000001
#define SYSDAP_BGR_REG_SYSDAP_GATING_MASK 0x0
#define SYSDAP_BGR_REG_SYSDAP_GATING_PASS 0x1

#define UART_BGR_REG 0x0000090c//UART Bus Gating Reset Register
#define UART_BGR_REG_UART7_RST_OFFSET 23
#define UART_BGR_REG_UART7_RST_CLEAR_MASK 0x00800000
#define UART_BGR_REG_UART7_RST_ASSERT 0x0
#define UART_BGR_REG_UART7_RST_DE_ASSERT 0x1
#define UART_BGR_REG_UART6_RST_OFFSET 22
#define UART_BGR_REG_UART6_RST_CLEAR_MASK 0x00400000
#define UART_BGR_REG_UART6_RST_ASSERT 0x0
#define UART_BGR_REG_UART6_RST_DE_ASSERT 0x1
#define UART_BGR_REG_UART5_RST_OFFSET 21
#define UART_BGR_REG_UART5_RST_CLEAR_MASK 0x00200000
#define UART_BGR_REG_UART5_RST_ASSERT 0x0
#define UART_BGR_REG_UART5_RST_DE_ASSERT 0x1
#define UART_BGR_REG_UART4_RST_OFFSET 20
#define UART_BGR_REG_UART4_RST_CLEAR_MASK 0x00100000
#define UART_BGR_REG_UART4_RST_ASSERT 0x0
#define UART_BGR_REG_UART4_RST_DE_ASSERT 0x1
#define UART_BGR_REG_UART3_RST_OFFSET 19
#define UART_BGR_REG_UART3_RST_CLEAR_MASK 0x00080000
#define UART_BGR_REG_UART3_RST_ASSERT 0x0
#define UART_BGR_REG_UART3_RST_DE_ASSERT 0x1
#define UART_BGR_REG_UART2_RST_OFFSET 18
#define UART_BGR_REG_UART2_RST_CLEAR_MASK 0x00040000
#define UART_BGR_REG_UART2_RST_ASSERT 0x0
#define UART_BGR_REG_UART2_RST_DE_ASSERT 0x1
#define UART_BGR_REG_UART1_RST_OFFSET 17
#define UART_BGR_REG_UART1_RST_CLEAR_MASK 0x00020000
#define UART_BGR_REG_UART1_RST_ASSERT 0x0
#define UART_BGR_REG_UART1_RST_DE_ASSERT 0x1
#define UART_BGR_REG_UART0_RST_OFFSET 16
#define UART_BGR_REG_UART0_RST_CLEAR_MASK 0x00010000
#define UART_BGR_REG_UART0_RST_ASSERT 0x0
#define UART_BGR_REG_UART0_RST_DE_ASSERT 0x1
#define UART_BGR_REG_UART7_GATING_OFFSET 7
#define UART_BGR_REG_UART7_GATING_CLEAR_MASK 0x00000080
#define UART_BGR_REG_UART7_GATING_MASK 0x0
#define UART_BGR_REG_UART7_GATING_PASS 0x1
#define UART_BGR_REG_UART6_GATING_OFFSET 6
#define UART_BGR_REG_UART6_GATING_CLEAR_MASK 0x00000040
#define UART_BGR_REG_UART6_GATING_MASK 0x0
#define UART_BGR_REG_UART6_GATING_PASS 0x1
#define UART_BGR_REG_UART5_GATING_OFFSET 5
#define UART_BGR_REG_UART5_GATING_CLEAR_MASK 0x00000020
#define UART_BGR_REG_UART5_GATING_MASK 0x0
#define UART_BGR_REG_UART5_GATING_PASS 0x1
#define UART_BGR_REG_UART4_GATING_OFFSET 4
#define UART_BGR_REG_UART4_GATING_CLEAR_MASK 0x00000010
#define UART_BGR_REG_UART4_GATING_MASK 0x0
#define UART_BGR_REG_UART4_GATING_PASS 0x1
#define UART_BGR_REG_UART3_GATING_OFFSET 3
#define UART_BGR_REG_UART3_GATING_CLEAR_MASK 0x00000008
#define UART_BGR_REG_UART3_GATING_MASK 0x0
#define UART_BGR_REG_UART3_GATING_PASS 0x1
#define UART_BGR_REG_UART2_GATING_OFFSET 2
#define UART_BGR_REG_UART2_GATING_CLEAR_MASK 0x00000004
#define UART_BGR_REG_UART2_GATING_MASK 0x0
#define UART_BGR_REG_UART2_GATING_PASS 0x1
#define UART_BGR_REG_UART1_GATING_OFFSET 1
#define UART_BGR_REG_UART1_GATING_CLEAR_MASK 0x00000002
#define UART_BGR_REG_UART1_GATING_MASK 0x0
#define UART_BGR_REG_UART1_GATING_PASS 0x1
#define UART_BGR_REG_UART0_GATING_OFFSET 0
#define UART_BGR_REG_UART0_GATING_CLEAR_MASK 0x00000001
#define UART_BGR_REG_UART0_GATING_MASK 0x0
#define UART_BGR_REG_UART0_GATING_PASS 0x1

#define TWI_BGR_REG 0x0000091c//TWI Bus Gating Reset Register
#define TWI_BGR_REG_TWI5_RST_OFFSET 21
#define TWI_BGR_REG_TWI5_RST_CLEAR_MASK 0x00200000
#define TWI_BGR_REG_TWI5_RST_ASSERT 0x0
#define TWI_BGR_REG_TWI5_RST_DE_ASSERT 0x1
#define TWI_BGR_REG_TWI4_RST_OFFSET 20
#define TWI_BGR_REG_TWI4_RST_CLEAR_MASK 0x00100000
#define TWI_BGR_REG_TWI4_RST_ASSERT 0x0
#define TWI_BGR_REG_TWI4_RST_DE_ASSERT 0x1
#define TWI_BGR_REG_TWI3_RST_OFFSET 19
#define TWI_BGR_REG_TWI3_RST_CLEAR_MASK 0x00080000
#define TWI_BGR_REG_TWI3_RST_ASSERT 0x0
#define TWI_BGR_REG_TWI3_RST_DE_ASSERT 0x1
#define TWI_BGR_REG_TWI2_RST_OFFSET 18
#define TWI_BGR_REG_TWI2_RST_CLEAR_MASK 0x00040000
#define TWI_BGR_REG_TWI2_RST_ASSERT 0x0
#define TWI_BGR_REG_TWI2_RST_DE_ASSERT 0x1
#define TWI_BGR_REG_TWI1_RST_OFFSET 17
#define TWI_BGR_REG_TWI1_RST_CLEAR_MASK 0x00020000
#define TWI_BGR_REG_TWI1_RST_ASSERT 0x0
#define TWI_BGR_REG_TWI1_RST_DE_ASSERT 0x1
#define TWI_BGR_REG_TWI0_RST_OFFSET 16
#define TWI_BGR_REG_TWI0_RST_CLEAR_MASK 0x00010000
#define TWI_BGR_REG_TWI0_RST_ASSERT 0x0
#define TWI_BGR_REG_TWI0_RST_DE_ASSERT 0x1
#define TWI_BGR_REG_TWI5_GATING_OFFSET 5
#define TWI_BGR_REG_TWI5_GATING_CLEAR_MASK 0x00000020
#define TWI_BGR_REG_TWI5_GATING_MASK 0x0
#define TWI_BGR_REG_TWI5_GATING_PASS 0x1
#define TWI_BGR_REG_TWI4_GATING_OFFSET 4
#define TWI_BGR_REG_TWI4_GATING_CLEAR_MASK 0x00000010
#define TWI_BGR_REG_TWI4_GATING_MASK 0x0
#define TWI_BGR_REG_TWI4_GATING_PASS 0x1
#define TWI_BGR_REG_TWI3_GATING_OFFSET 3
#define TWI_BGR_REG_TWI3_GATING_CLEAR_MASK 0x00000008
#define TWI_BGR_REG_TWI3_GATING_MASK 0x0
#define TWI_BGR_REG_TWI3_GATING_PASS 0x1
#define TWI_BGR_REG_TWI2_GATING_OFFSET 2
#define TWI_BGR_REG_TWI2_GATING_CLEAR_MASK 0x00000004
#define TWI_BGR_REG_TWI2_GATING_MASK 0x0
#define TWI_BGR_REG_TWI2_GATING_PASS 0x1
#define TWI_BGR_REG_TWI1_GATING_OFFSET 1
#define TWI_BGR_REG_TWI1_GATING_CLEAR_MASK 0x00000002
#define TWI_BGR_REG_TWI1_GATING_MASK 0x0
#define TWI_BGR_REG_TWI1_GATING_PASS 0x1
#define TWI_BGR_REG_TWI0_GATING_OFFSET 0
#define TWI_BGR_REG_TWI0_GATING_CLEAR_MASK 0x00000001
#define TWI_BGR_REG_TWI0_GATING_MASK 0x0
#define TWI_BGR_REG_TWI0_GATING_PASS 0x1

#define CAN_BGR_REG 0x0000092c//CAN Bus Gating Reset Register
#define CAN_BGR_REG_CAN0_RST_OFFSET 16
#define CAN_BGR_REG_CAN0_RST_CLEAR_MASK 0x00010000
#define CAN_BGR_REG_CAN0_RST_ASSERT 0x0
#define CAN_BGR_REG_CAN0_RST_DE_ASSERT 0x1
#define CAN_BGR_REG_CAN0_GATING_OFFSET 0
#define CAN_BGR_REG_CAN0_GATING_CLEAR_MASK 0x00000001
#define CAN_BGR_REG_CAN0_GATING_MASK 0x0
#define CAN_BGR_REG_CAN0_GATING_PASS 0x1

/*#define SPI0_CLK_REG 0x00000940*///SPI0 Clock Register
#define SPI0_CLK_REG_SPI0_CLK_GATING_OFFSET 31
#define SPI0_CLK_REG_SPI0_CLK_GATING_CLEAR_MASK 0x80000000
#define SPI0_CLK_REG_SPI0_CLK_GATING_CLOCK_IS_OFF 0x0
#define SPI0_CLK_REG_SPI0_CLK_GATING_CLOCK_IS_ON 0x1
#define SPI0_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define SPI0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define SPI0_CLK_REG_CLK_SRC_SEL_HOSC 0x000
#define SPI0_CLK_REG_CLK_SRC_SEL_PERI0_300M 0x001
#define SPI0_CLK_REG_CLK_SRC_SEL_PERI0_200M 0x010
#define SPI0_CLK_REG_CLK_SRC_SEL_PERI1_300M 0x011
#define SPI0_CLK_REG_CLK_SRC_SEL_PERI1_200M 0x100
#define SPI0_CLK_REG_FACTOR_M_OFFSET 0
#define SPI0_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define SPI1_CLK_REG 0x00000944//SPI1 Clock Register
#define SPI1_CLK_REG_SPI1_CLK_GATING_OFFSET 31
#define SPI1_CLK_REG_SPI1_CLK_GATING_CLEAR_MASK 0x80000000
#define SPI1_CLK_REG_SPI1_CLK_GATING_CLOCK_IS_OFF 0x0
#define SPI1_CLK_REG_SPI1_CLK_GATING_CLOCK_IS_ON 0x1
#define SPI1_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define SPI1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define SPI1_CLK_REG_CLK_SRC_SEL_HOSC 0x000
#define SPI1_CLK_REG_CLK_SRC_SEL_PERI0_300M 0x001
#define SPI1_CLK_REG_CLK_SRC_SEL_PERI0_200M 0x010
#define SPI1_CLK_REG_CLK_SRC_SEL_PERI1_300M 0x011
#define SPI1_CLK_REG_CLK_SRC_SEL_PERI1_200M 0x100
#define SPI1_CLK_REG_FACTOR_M_OFFSET 0
#define SPI1_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define SPI2_CLK_REG 0x00000948//SPI2 Clock Register
#define SPI2_CLK_REG_SPI2_CLK_GATING_OFFSET 31
#define SPI2_CLK_REG_SPI2_CLK_GATING_CLEAR_MASK 0x80000000
#define SPI2_CLK_REG_SPI2_CLK_GATING_CLOCK_IS_OFF 0x0
#define SPI2_CLK_REG_SPI2_CLK_GATING_CLOCK_IS_ON 0x1
#define SPI2_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define SPI2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define SPI2_CLK_REG_CLK_SRC_SEL_HOSC 0x000
#define SPI2_CLK_REG_CLK_SRC_SEL_PERI0_300M 0x001
#define SPI2_CLK_REG_CLK_SRC_SEL_PERI0_200M 0x010
#define SPI2_CLK_REG_CLK_SRC_SEL_PERI1_300M 0x011
#define SPI2_CLK_REG_CLK_SRC_SEL_PERI1_200M 0x100
#define SPI2_CLK_REG_FACTOR_M_OFFSET 0
#define SPI2_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define SPIF_CLK_REG 0x00000950//SPIF Clock Register
#define SPIF_CLK_REG_SPIF_CLK_GATING_OFFSET 31
#define SPIF_CLK_REG_SPIF_CLK_GATING_CLEAR_MASK 0x80000000
#define SPIF_CLK_REG_SPIF_CLK_GATING_CLOCK_IS_OFF 0x0
#define SPIF_CLK_REG_SPIF_CLK_GATING_CLOCK_IS_ON 0x1
#define SPIF_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define SPIF_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define SPIF_CLK_REG_CLK_SRC_SEL_HOSC 0x000
#define SPIF_CLK_REG_CLK_SRC_SEL_PERI0_200M 0x001
#define SPIF_CLK_REG_CLK_SRC_SEL_PERI0_300M 0x010
#define SPIF_CLK_REG_CLK_SRC_SEL_PERI1_200M 0x011
#define SPIF_CLK_REG_CLK_SRC_SEL_PERI1_300M 0x100
#define SPIF_CLK_REG_FACTOR_N_OFFSET 8
#define SPIF_CLK_REG_FACTOR_N_CLEAR_MASK 0x00001f00
#define SPIF_CLK_REG_FACTOR_M_OFFSET 0
#define SPIF_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define SPI_BGR_REG 0x0000096c//SPI Bus Gating Reset Register
#define SPI_BGR_REG_SPIF_RST_OFFSET 19
#define SPI_BGR_REG_SPIF_RST_CLEAR_MASK 0x00080000
#define SPI_BGR_REG_SPIF_RST_ASSERT 0x0
#define SPI_BGR_REG_SPIF_RST_DE_ASSERT 0x1
#define SPI_BGR_REG_SPI2_RST_OFFSET 18
#define SPI_BGR_REG_SPI2_RST_CLEAR_MASK 0x00040000
#define SPI_BGR_REG_SPI2_RST_ASSERT 0x0
#define SPI_BGR_REG_SPI2_RST_DE_ASSERT 0x1
#define SPI_BGR_REG_SPI1_RST_OFFSET 17
#define SPI_BGR_REG_SPI1_RST_CLEAR_MASK 0x00020000
#define SPI_BGR_REG_SPI1_RST_ASSERT 0x0
#define SPI_BGR_REG_SPI1_RST_DE_ASSERT 0x1
#define SPI_BGR_REG_SPI0_RST_OFFSET 16
#define SPI_BGR_REG_SPI0_RST_CLEAR_MASK 0x00010000
#define SPI_BGR_REG_SPI0_RST_ASSERT 0x0
#define SPI_BGR_REG_SPI0_RST_DE_ASSERT 0x1
#define SPI_BGR_REG_SPIF_GATING_OFFSET 3
#define SPI_BGR_REG_SPIF_GATING_CLEAR_MASK 0x00000008
#define SPI_BGR_REG_SPIF_GATING_MASK 0x0
#define SPI_BGR_REG_SPIF_GATING_PASS 0x1
#define SPI_BGR_REG_SPI2_GATING_OFFSET 2
#define SPI_BGR_REG_SPI2_GATING_CLEAR_MASK 0x00000004
#define SPI_BGR_REG_SPI2_GATING_MASK 0x0
#define SPI_BGR_REG_SPI2_GATING_PASS 0x1
#define SPI_BGR_REG_SPI1_GATING_OFFSET 1
#define SPI_BGR_REG_SPI1_GATING_CLEAR_MASK 0x00000002
#define SPI_BGR_REG_SPI1_GATING_MASK 0x0
#define SPI_BGR_REG_SPI1_GATING_PASS 0x1
#define SPI_BGR_REG_SPI0_GATING_OFFSET 0
#define SPI_BGR_REG_SPI0_GATING_CLEAR_MASK 0x00000001
#define SPI_BGR_REG_SPI0_GATING_MASK 0x0
#define SPI_BGR_REG_SPI0_GATING_PASS 0x1

#define GMAC0_25M_CLK_REG 0x00000970//GMAC0_25M Clock Register
#define GMAC0_25M_CLK_REG_GMAC0_25M_CLK_GATING_OFFSET 31
#define GMAC0_25M_CLK_REG_GMAC0_25M_CLK_GATING_CLEAR_MASK 0x80000000
#define GMAC0_25M_CLK_REG_GMAC0_25M_CLK_GATING_CLOCK_IS_OFF 0x0
#define GMAC0_25M_CLK_REG_GMAC0_25M_CLK_GATING_CLOCK_IS_ON 0x1
#define GMAC0_25M_CLK_REG_GMAC0_25M_CLK_SRC_GATING_OFFSET 30
#define GMAC0_25M_CLK_REG_GMAC0_25M_CLK_SRC_GATING_CLEAR_MASK 0x40000000
#define GMAC0_25M_CLK_REG_GMAC0_25M_CLK_SRC_GATING_CLOCK_IS_OFF 0x0
#define GMAC0_25M_CLK_REG_GMAC0_25M_CLK_SRC_GATING_CLOCK_IS_ON 0x1

#define GMAC1_25M_CLK_REG 0x00000974//GMAC1_25M Clock Register
#define GMAC1_25M_CLK_REG_GMAC1_25M_CLK_GATING_OFFSET 31
#define GMAC1_25M_CLK_REG_GMAC1_25M_CLK_GATING_CLEAR_MASK 0x80000000
#define GMAC1_25M_CLK_REG_GMAC1_25M_CLK_GATING_CLOCK_IS_OFF 0x0
#define GMAC1_25M_CLK_REG_GMAC1_25M_CLK_GATING_CLOCK_IS_ON 0x1
#define GMAC1_25M_CLK_REG_GMAC1_25M_CLK_SRC_GATING_OFFSET 30
#define GMAC1_25M_CLK_REG_GMAC1_25M_CLK_SRC_GATING_CLEAR_MASK 0x40000000
#define GMAC1_25M_CLK_REG_GMAC1_25M_CLK_SRC_GATING_CLOCK_IS_OFF 0x0
#define GMAC1_25M_CLK_REG_GMAC1_25M_CLK_SRC_GATING_CLOCK_IS_ON 0x1

#define GMAC_BGR_REG 0x0000097c//GMAC Bus Gating Reset Register
#define GMAC_BGR_REG_GMAC1_RST_OFFSET 17
#define GMAC_BGR_REG_GMAC1_RST_CLEAR_MASK 0x00020000
#define GMAC_BGR_REG_GMAC1_RST_ASSERT 0x0
#define GMAC_BGR_REG_GMAC1_RST_DE_ASSERT 0x1
#define GMAC_BGR_REG_GMAC0_RST_OFFSET 16
#define GMAC_BGR_REG_GMAC0_RST_CLEAR_MASK 0x00010000
#define GMAC_BGR_REG_GMAC0_RST_ASSERT 0x0
#define GMAC_BGR_REG_GMAC0_RST_DE_ASSERT 0x1
#define GMAC_BGR_REG_GMAC1_GATING_OFFSET 1
#define GMAC_BGR_REG_GMAC1_GATING_CLEAR_MASK 0x00000002
#define GMAC_BGR_REG_GMAC1_GATING_MASKS 0x0
#define GMAC_BGR_REG_GMAC1_GATING_PASS 0x1
#define GMAC_BGR_REG_GMAC0_GATING_OFFSET 0
#define GMAC_BGR_REG_GMAC0_GATING_CLEAR_MASK 0x00000001
#define GMAC_BGR_REG_GMAC0_GATING_MASK 0x0
#define GMAC_BGR_REG_GMAC0_GATING_PASS 0x1

#define IRRX_CLK_REG 0x00000990//IRRX Clock Register
#define IRRX_CLK_REG_IRRX_CLK_GATING_OFFSET 31
#define IRRX_CLK_REG_IRRX_CLK_GATING_CLEAR_MASK 0x80000000
#define IRRX_CLK_REG_IRRX_CLK_GATING_CLOCK_IS_OFF 0x0
#define IRRX_CLK_REG_IRRX_CLK_GATING_CLOCK_IS_ON 0x1
#define IRRX_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define IRRX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x01000000
#define IRRX_CLK_REG_CLK_SRC_SEL_CLK32K 0x0
#define IRRX_CLK_REG_CLK_SRC_SEL_HOSC 0x1
#define IRRX_CLK_REG_FACTOR_M_OFFSET 0
#define IRRX_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define IRRX_BGR_REG 0x0000099c//IRRX Bus Gating Reset Register
#define IRRX_BGR_REG_IRRX_RST_OFFSET 16
#define IRRX_BGR_REG_IRRX_RST_CLEAR_MASK 0x00010000
#define IRRX_BGR_REG_IRRX_RST_ASSERT 0x0
#define IRRX_BGR_REG_IRRX_RST_DE_ASSERT 0x1
#define IRRX_BGR_REG_IRRX_GATING_OFFSET 0
#define IRRX_BGR_REG_IRRX_GATING_CLEAR_MASK 0x00000001
#define IRRX_BGR_REG_IRRX_GATING_MASK 0x0
#define IRRX_BGR_REG_IRRX_GATING_PASS 0x1

#define IRTX_CLK_REG 0x000009c0//IRTX Clock Register
#define IRTX_CLK_REG_IRTX_CLK_GATING_OFFSET 31
#define IRTX_CLK_REG_IRTX_CLK_GATING_CLEAR_MASK 0x80000000
#define IRTX_CLK_REG_IRTX_CLK_GATING_CLOCK_IS_OFF 0x0
#define IRTX_CLK_REG_IRTX_CLK_GATING_CLOCK_IS_ON 0x1
#define IRTX_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define IRTX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define IRTX_CLK_REG_CLK_SRC_SEL_HOSC 0x0
#define IRTX_CLK_REG_CLK_SRC_SEL_PERI1_600M 0x1
#define IRTX_CLK_REG_FACTOR_M_OFFSET 0
#define IRTX_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define IRTX_BGR_REG 0x000009cc//IRTX Bus Gating Reset Register
#define IRTX_BGR_REG_IRTX_RST_OFFSET 16
#define IRTX_BGR_REG_IRTX_RST_CLEAR_MASK 0x00010000
#define IRTX_BGR_REG_IRTX_RST_ASSERT 0x0
#define IRTX_BGR_REG_IRTX_RST_DE_ASSERT 0x1
#define IRTX_BGR_REG_IRTX_GATING_OFFSET 0
#define IRTX_BGR_REG_IRTX_GATING_CLEAR_MASK 0x00000001
#define IRTX_BGR_REG_IRTX_GATING_MASK 0x0
#define IRTX_BGR_REG_IRTX_GATING_PASS 0x1

#define GPADC_24M_CLK_REG 0x000009e0//GPADC_24M Clock Register
#define GPADC_24M_CLK_REG_GPADC_24M_CLK_GATING_OFFSET 31
#define GPADC_24M_CLK_REG_GPADC_24M_CLK_GATING_CLEAR_MASK 0x80000000
#define GPADC_24M_CLK_REG_GPADC_24M_CLK_GATING_CLOCK_IS_OFF 0x0
#define GPADC_24M_CLK_REG_GPADC_24M_CLK_GATING_CLOCK_IS_ON 0x1
#define GPADC_24M_CLK_REG_FACTOR_M_OFFSET 0
#define GPADC_24M_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define GPADC_BGR_REG 0x000009ec//GPADC Bus Gating Reset Register
#define GPADC_BGR_REG_GPADC_RST_OFFSET 16
#define GPADC_BGR_REG_GPADC_RST_CLEAR_MASK 0x00010000
#define GPADC_BGR_REG_GPADC_RST_ASSERT 0x0
#define GPADC_BGR_REG_GPADC_RST_DE_ASSERT 0x1
#define GPADC_BGR_REG_GPADC_GATING_OFFSET 0
#define GPADC_BGR_REG_GPADC_GATING_CLEAR_MASK 0x00000001
#define GPADC_BGR_REG_GPADC_GATING_MASK 0x0
#define GPADC_BGR_REG_GPADC_GATING_PASS 0x1

#define THS_BGR_REG 0x000009fc//THS Bus Gating Reset Register
#define THS_BGR_REG_THS_RST_OFFSET 16
#define THS_BGR_REG_THS_RST_CLEAR_MASK 0x00010000
#define THS_BGR_REG_THS_RST_ASSERT 0x0
#define THS_BGR_REG_THS_RST_DE_ASSERT 0x1
#define THS_BGR_REG_THS_GATING_OFFSET 0
#define THS_BGR_REG_THS_GATING_CLEAR_MASK 0x00000001
#define THS_BGR_REG_THS_GATING_MASK 0x0
#define THS_BGR_REG_THS_GATING_PASS 0x1

#define USB0_CLK_REG 0x00000a70//USB0 Clock Register
#define USB0_CLK_REG_USB0_CLKEN_OFFSET 31
#define USB0_CLK_REG_USB0_CLKEN_CLEAR_MASK 0x80000000
#define USB0_CLK_REG_USB0_CLKEN_CLOCK_IS_OFF 0x0
#define USB0_CLK_REG_USB0_CLKEN_CLOCK_IS_ON 0x1
#define USB0_CLK_REG_USBPHY0_RSTN_OFFSET 30
#define USB0_CLK_REG_USBPHY0_RSTN_CLEAR_MASK 0x40000000
#define USB0_CLK_REG_USBPHY0_RSTN_ASSERT 0x0
#define USB0_CLK_REG_USBPHY0_RSTN_DE_ASSERT 0x1
#define USB0_CLK_REG_USB0_CLK12M_SEL_OFFSET 24
#define USB0_CLK_REG_USB0_CLK12M_SEL_CLEAR_MASK 0x03000000
#define USB0_CLK_REG_USB0_CLK12M_SEL_12M_DIVIDED_FROM_48MHZ 0x00
#define USB0_CLK_REG_USB0_CLK12M_SEL_12M_DIVIDED_FROM_24MHZ 0x01
#define USB0_CLK_REG_USB0_CLK12M_SEL_RTC_32K 0x10

#define USB1_CLK_REG 0x00000a74//USB1 Clock Register
#define USB1_CLK_REG_USB1_CLKEN_OFFSET 31
#define USB1_CLK_REG_USB1_CLKEN_CLEAR_MASK 0x80000000
#define USB1_CLK_REG_USB1_CLKEN_CLOCK_IS_OFF 0x0
#define USB1_CLK_REG_USB1_CLKEN_CLOCK_IS_ON 0x1
#define USB1_CLK_REG_USBPHY1_RSTN_OFFSET 30
#define USB1_CLK_REG_USBPHY1_RSTN_CLEAR_MASK 0x40000000
#define USB1_CLK_REG_USBPHY1_RSTN_ASSERT 0x0
#define USB1_CLK_REG_USBPHY1_RSTN_DE_ASSERT 0x1
#define USB1_CLK_REG_USB1_CLK12M_SEL_OFFSET 24
#define USB1_CLK_REG_USB1_CLK12M_SEL_CLEAR_MASK 0x03000000
#define USB1_CLK_REG_USB1_CLK12M_SEL_12M_DIVIDED_FROM_48MHZ 0x00
#define USB1_CLK_REG_USB1_CLK12M_SEL_12M_DIVIDED_FROM_24MHZ 0x01
#define USB1_CLK_REG_USB1_CLK12M_SEL_RTC_32K 0x10

#define USB2_REF_CLK_REG 0x00000a78//USB2_REF Clock Register
#define USB2_REF_CLK_REG_USB2_REF_CLK_GATING_OFFSET 31
#define USB2_REF_CLK_REG_USB2_REF_CLK_GATING_CLEAR_MASK 0x80000000
#define USB2_REF_CLK_REG_USB2_REF_CLK_GATING_CLOCK_IS_OFF 0x0
#define USB2_REF_CLK_REG_USB2_REF_CLK_GATING_CLOCK_IS_ON 0x1

#define USB2_SUSPEND_CLK_REG 0x00000a7c//USB2_SUSPEND Clock Register
#define USB2_SUSPEND_CLK_REG_USB2_SUSPEND_CLK_GATING_OFFSET 31
#define USB2_SUSPEND_CLK_REG_USB2_SUSPEND_CLK_GATING_CLEAR_MASK 0x80000000
#define USB2_SUSPEND_CLK_REG_USB2_SUSPEND_CLK_GATING_CLOCK_IS_OFF 0x0
#define USB2_SUSPEND_CLK_REG_USB2_SUSPEND_CLK_GATING_CLOCK_IS_ON 0x1

#define USB_BGR_REG 0x00000a8c//USB Bus Gating Reset Register
#define USB_BGR_REG_USB2_PHY_RST_OFFSET 26
#define USB_BGR_REG_USB2_PHY_RST_CLEAR_MASK 0x04000000
#define USB_BGR_REG_USB2_PHY_RST_ASSERT 0x0
#define USB_BGR_REG_USB2_PHY_RST_DE_ASSERT 0x1
#define USB_BGR_REG_USB2_RST_OFFSET 25
#define USB_BGR_REG_USB2_RST_CLEAR_MASK 0x02000000
#define USB_BGR_REG_USB2_RST_ASSERT 0x0
#define USB_BGR_REG_USB2_RST_DE_ASSERT 0x1
#define USB_BGR_REG_USBOTG0_RST_OFFSET 24
#define USB_BGR_REG_USBOTG0_RST_CLEAR_MASK 0x01000000
#define USB_BGR_REG_USBOTG0_RST_ASSERT 0x0
#define USB_BGR_REG_USBOTG0_RST_DE_ASSERT 0x1
#define USB_BGR_REG_USBEHCI1_RST_OFFSET 21
#define USB_BGR_REG_USBEHCI1_RST_CLEAR_MASK 0x00200000
#define USB_BGR_REG_USBEHCI1_RST_ASSERT 0x0
#define USB_BGR_REG_USBEHCI1_RST_DE_ASSERT 0x1
#define USB_BGR_REG_USBEHCI0_RST_OFFSET 20
#define USB_BGR_REG_USBEHCI0_RST_CLEAR_MASK 0x00100000
#define USB_BGR_REG_USBEHCI0_RST_ASSERT 0x0
#define USB_BGR_REG_USBEHCI0_RST_DE_ASSERT 0x1
#define USB_BGR_REG_USBOHCI1_RST_OFFSET 17
#define USB_BGR_REG_USBOHCI1_RST_CLEAR_MASK 0x00020000
#define USB_BGR_REG_USBOHCI1_RST_ASSERT 0x0
#define USB_BGR_REG_USBOHCI1_RST_DE_ASSERT 0x1
#define USB_BGR_REG_USBOHCI0_RST_OFFSET 16
#define USB_BGR_REG_USBOHCI0_RST_CLEAR_MASK 0x00010000
#define USB_BGR_REG_USBOHCI0_RST_ASSERT 0x0
#define USB_BGR_REG_USBOHCI0_RST_DE_ASSERT 0x1
#define USB_BGR_REG_USB2_GATING_OFFSET 9
#define USB_BGR_REG_USB2_GATING_CLEAR_MASK 0x00000200
#define USB_BGR_REG_USB2_GATING_MASK 0x0
#define USB_BGR_REG_USB2_GATING_PASS 0x1
#define USB_BGR_REG_USBOTG0_GATING_OFFSET 8
#define USB_BGR_REG_USBOTG0_GATING_CLEAR_MASK 0x00000100
#define USB_BGR_REG_USBOTG0_GATING_MASK 0x0
#define USB_BGR_REG_USBOTG0_GATING_PASS 0x1
#define USB_BGR_REG_USBEHCI1_GATING_OFFSET 5
#define USB_BGR_REG_USBEHCI1_GATING_CLEAR_MASK 0x00000020
#define USB_BGR_REG_USBEHCI1_GATING_MASK 0x0
#define USB_BGR_REG_USBEHCI1_GATING_PASS 0x1
#define USB_BGR_REG_USBEHCI0_GATING_OFFSET 4
#define USB_BGR_REG_USBEHCI0_GATING_CLEAR_MASK 0x00000010
#define USB_BGR_REG_USBEHCI0_GATING_MASK 0x0
#define USB_BGR_REG_USBEHCI0_GATING_PASS 0x1
#define USB_BGR_REG_USBOHCI1_GATING_OFFSET 1
#define USB_BGR_REG_USBOHCI1_GATING_CLEAR_MASK 0x00000002
#define USB_BGR_REG_USBOHCI1_GATING_MASK 0x0
#define USB_BGR_REG_USBOHCI1_GATING_PASS 0x1
#define USB_BGR_REG_USBOHCI0_GATING_OFFSET 0
#define USB_BGR_REG_USBOHCI0_GATING_CLEAR_MASK 0x00000001
#define USB_BGR_REG_USBOHCI0_GATING_MASK 0x0
#define USB_BGR_REG_USBOHCI0_GATING_PASS 0x1

#define LRADC_BGR_REG 0x00000a9c//LRADC Bus Gating Reset Register
#define LRADC_BGR_REG_LRADC_RST_OFFSET 16
#define LRADC_BGR_REG_LRADC_RST_CLEAR_MASK 0x00010000
#define LRADC_BGR_REG_LRADC_RST_ASSERT 0x0
#define LRADC_BGR_REG_LRADC_RST_DE_ASSERT 0x1
#define LRADC_BGR_REG_LRADC_GATING_OFFSET 0
#define LRADC_BGR_REG_LRADC_GATING_CLEAR_MASK 0x00000001
#define LRADC_BGR_REG_LRADC_GATING_MASK 0x0
#define LRADC_BGR_REG_LRADC_GATING_PASS 0x1

#define PCIE_AUX_CLK_REG 0x00000aa0//PCIE_AUX Clock Register
#define PCIE_AUX_CLK_REG_PCIE_AUX_CLK_GATING_OFFSET 31
#define PCIE_AUX_CLK_REG_PCIE_AUX_CLK_GATING_CLEAR_MASK 0x80000000
#define PCIE_AUX_CLK_REG_PCIE_AUX_CLK_GATING_CLOCK_IS_OFF 0x0
#define PCIE_AUX_CLK_REG_PCIE_AUX_CLK_GATING_CLOCK_IS_ON 0x1
#define PCIE_AUX_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define PCIE_AUX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x01000000
#define PCIE_AUX_CLK_REG_CLK_SRC_SEL_HOSC 0x0
#define PCIE_AUX_CLK_REG_CLK_SRC_SEL_CLK32K 0x1
#define PCIE_AUX_CLK_REG_FACTOR_M_OFFSET 0
#define PCIE_AUX_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define PCIE_REF_CLK_REG 0x00000aa4//PCIE_REF Clock Register
#define PCIE_REF_CLK_REG_PCIE_REF_CLK_GATING_OFFSET 31
#define PCIE_REF_CLK_REG_PCIE_REF_CLK_GATING_CLEAR_MASK 0x80000000
#define PCIE_REF_CLK_REG_PCIE_REF_CLK_GATING_CLOCK_IS_OFF 0x0
#define PCIE_REF_CLK_REG_PCIE_REF_CLK_GATING_CLOCK_IS_ON 0x1

#define PCIE_BGR_REG 0x00000aac//PCIE Bus Gating Reset Register
#define PCIE_BGR_REG_PCIE_PE_RST_OFFSET 18
#define PCIE_BGR_REG_PCIE_PE_RST_CLEAR_MASK 0x00040000
#define PCIE_BGR_REG_PCIE_PE_RST_ASSERT 0x0
#define PCIE_BGR_REG_PCIE_PE_RST_DE_ASSERT 0x1
#define PCIE_BGR_REG_PCIE_POWER_UP_RST_OFFSET 17
#define PCIE_BGR_REG_PCIE_POWER_UP_RST_CLEAR_MASK 0x00020000
#define PCIE_BGR_REG_PCIE_POWER_UP_RST_ASSERT 0x0
#define PCIE_BGR_REG_PCIE_POWER_UP_RST_DE_ASSERT 0x1
#define PCIE_BGR_REG_PCIE_RST_OFFSET 16
#define PCIE_BGR_REG_PCIE_RST_CLEAR_MASK 0x00010000
#define PCIE_BGR_REG_PCIE_RST_ASSERT 0x0
#define PCIE_BGR_REG_PCIE_RST_DE_ASSERT 0x1
#define PCIE_BGR_REG_PCIE_GATING_OFFSET 0
#define PCIE_BGR_REG_PCIE_GATING_CLEAR_MASK 0x00000001
#define PCIE_BGR_REG_PCIE_GATING_MASK 0x0
#define PCIE_BGR_REG_PCIE_GATING_PASS 0x1

#define DPSS_TOP0_BGR_REG 0x00000abc//DPSS_TOP0 Bus Gating Reset Register
#define DPSS_TOP0_BGR_REG_DPSS_TOP0_RST_OFFSET 16
#define DPSS_TOP0_BGR_REG_DPSS_TOP0_RST_CLEAR_MASK 0x00010000
#define DPSS_TOP0_BGR_REG_DPSS_TOP0_RST_ASSERT 0x0
#define DPSS_TOP0_BGR_REG_DPSS_TOP0_RST_DE_ASSERT 0x1
#define DPSS_TOP0_BGR_REG_DPSS_TOP0_GATING_OFFSET 0
#define DPSS_TOP0_BGR_REG_DPSS_TOP0_GATING_CLEAR_MASK 0x00000001
#define DPSS_TOP0_BGR_REG_DPSS_TOP0_GATING_MASK 0x0
#define DPSS_TOP0_BGR_REG_DPSS_TOP0_GATING_PASS 0x1

#define DPSS_TOP1_BGR_REG 0x00000acc//DPSS_TOP1 Bus Gating Reset Register
#define DPSS_TOP1_BGR_REG_DPSS_TOP1_RST_OFFSET 16
#define DPSS_TOP1_BGR_REG_DPSS_TOP1_RST_CLEAR_MASK 0x00010000
#define DPSS_TOP1_BGR_REG_DPSS_TOP1_RST_ASSERT 0x0
#define DPSS_TOP1_BGR_REG_DPSS_TOP1_RST_DE_ASSERT 0x1
#define DPSS_TOP1_BGR_REG_DPSS_TOP1_GATING_OFFSET 0
#define DPSS_TOP1_BGR_REG_DPSS_TOP1_GATING_CLEAR_MASK 0x00000001
#define DPSS_TOP1_BGR_REG_DPSS_TOP1_GATING_MASK 0x0
#define DPSS_TOP1_BGR_REG_DPSS_TOP1_GATING_PASS 0x1

#define HDMI_24M_CLK_REG 0x00000b04//HDMI_24M Clock Register
#define HDMI_24M_CLK_REG_HDMI_24M_CLK_GATING_OFFSET 31
#define HDMI_24M_CLK_REG_HDMI_24M_CLK_GATING_CLEAR_MASK 0x80000000
#define HDMI_24M_CLK_REG_HDMI_24M_CLK_GATING_CLOCK_IS_OFF 0x0
#define HDMI_24M_CLK_REG_HDMI_24M_CLK_GATING_CLOCK_IS_ON 0x1

#define HDMI_CEC_CLK_REG 0x00000b10//HDMI CEC Clock Register
#define HDMI_CEC_CLK_REG_HDMI_CEC_CLK_GATING_OFFSET 31
#define HDMI_CEC_CLK_REG_HDMI_CEC_CLK_GATING_CLEAR_MASK 0x80000000
#define HDMI_CEC_CLK_REG_HDMI_CEC_CLK_GATING_CLOCK_IS_OFF 0x0
#define HDMI_CEC_CLK_REG_HDMI_CEC_CLK_GATING_CLOCK_IS_ON 0x1
#define HDMI_CEC_CLK_REG_PERI_GATING_OFFSET 30
#define HDMI_CEC_CLK_REG_PERI_GATING_CLEAR_MASK 0x40000000
#define HDMI_CEC_CLK_REG_PERI_GATING_CLOCK_IS_OFF 0x0
#define HDMI_CEC_CLK_REG_PERI_GATING_CLOCK_IS_ON 0x1
#define HDMI_CEC_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define HDMI_CEC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x01000000
#define HDMI_CEC_CLK_REG_CLK_SRC_SEL_CLK32K 0x0
#define HDMI_CEC_CLK_REG_CLK_SRC_SEL_HDMI_CEC_CLK32K__PLL_PERI_2X__36621___32_768KHZ 0x1

#define HDMI_BGR_REG 0x00000b1c//HDMI Bus Gating Reset Register
#define HDMI_BGR_REG_HDMI_SUB_RST_OFFSET 17
#define HDMI_BGR_REG_HDMI_SUB_RST_CLEAR_MASK 0x00020000
#define HDMI_BGR_REG_HDMI_SUB_RST_ASSERT 0x0
#define HDMI_BGR_REG_HDMI_SUB_RST_DE_ASSERT 0x1
#define HDMI_BGR_REG_HDMI_MAIN_RST_OFFSET 16
#define HDMI_BGR_REG_HDMI_MAIN_RST_CLEAR_MASK 0x00010000
#define HDMI_BGR_REG_HDMI_MAIN_RST_ASSERT 0x0
#define HDMI_BGR_REG_HDMI_MAIN_RST_DE_ASSERT 0x1
#define HDMI_BGR_REG_HDMI_GATING_OFFSET 0
#define HDMI_BGR_REG_HDMI_GATING_CLEAR_MASK 0x00000001
#define HDMI_BGR_REG_HDMI_GATING_MASK 0x0
#define HDMI_BGR_REG_HDMI_GATING_PASS 0x1

#define DSI0_CLK_REG 0x00000b24//DSI0 Clock Register
#define DSI0_CLK_REG_DSI0_CLK_GATING_OFFSET 31
#define DSI0_CLK_REG_DSI0_CLK_GATING_CLEAR_MASK 0x80000000
#define DSI0_CLK_REG_DSI0_CLK_GATING_CLOCK_IS_OFF 0x0
#define DSI0_CLK_REG_DSI0_CLK_GATING_CLOCK_IS_ON 0x1
#define DSI0_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define DSI0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define DSI0_CLK_REG_CLK_SRC_SEL_HOSC 0x000
#define DSI0_CLK_REG_CLK_SRC_SEL_PERI0_200M 0x001
#define DSI0_CLK_REG_CLK_SRC_SEL_PERI0_150M 0x010
#define DSI0_CLK_REG_FACTOR_M_OFFSET 0
#define DSI0_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define DSI1_CLK_REG 0x00000b28//DSI1 Clock Register
#define DSI1_CLK_REG_DSI1_CLK_GATING_OFFSET 31
#define DSI1_CLK_REG_DSI1_CLK_GATING_CLEAR_MASK 0x80000000
#define DSI1_CLK_REG_DSI1_CLK_GATING_CLOCK_IS_OFF 0x0
#define DSI1_CLK_REG_DSI1_CLK_GATING_CLOCK_IS_ON 0x1
#define DSI1_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define DSI1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define DSI1_CLK_REG_CLK_SRC_SEL_HOSC 0x000
#define DSI1_CLK_REG_CLK_SRC_SEL_PERI0_200M 0x001
#define DSI1_CLK_REG_CLK_SRC_SEL_PERI0_150M 0x010
#define DSI1_CLK_REG_FACTOR_M_OFFSET 0
#define DSI1_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define DSI_BGR_REG 0x00000b4c//DSI Bus Gating Reset Register
#define DSI_BGR_REG_DSI1_RST_OFFSET 17
#define DSI_BGR_REG_DSI1_RST_CLEAR_MASK 0x00020000
#define DSI_BGR_REG_DSI1_RST_ASSERT 0x0
#define DSI_BGR_REG_DSI1_RST_DE_ASSERT 0x1
#define DSI_BGR_REG_DSI0_RST_OFFSET 16
#define DSI_BGR_REG_DSI0_RST_CLEAR_MASK 0x00010000
#define DSI_BGR_REG_DSI0_RST_ASSERT 0x0
#define DSI_BGR_REG_DSI0_RST_DE_ASSERT 0x1
#define DSI_BGR_REG_DSI1_GATING_OFFSET 1
#define DSI_BGR_REG_DSI1_GATING_CLEAR_MASK 0x00000002
#define DSI_BGR_REG_DSI1_GATING_MASK 0x0
#define DSI_BGR_REG_DSI1_GATING_PASS 0x1
#define DSI_BGR_REG_DSI0_GATING_OFFSET 0
#define DSI_BGR_REG_DSI0_GATING_CLEAR_MASK 0x00000001
#define DSI_BGR_REG_DSI0_GATING_MASK 0x0
#define DSI_BGR_REG_DSI0_GATING_PASS 0x1

#define VO0_TCONLCD0_CLK_REG 0x00000b60//VO0_TCONLCD0 Clock Register
#define VO0_TCONLCD0_CLK_REG_VO0_TCONLCD0_CLK_GATING_OFFSET 31
#define VO0_TCONLCD0_CLK_REG_VO0_TCONLCD0_CLK_GATING_CLEAR_MASK 0x80000000
#define VO0_TCONLCD0_CLK_REG_VO0_TCONLCD0_CLK_GATING_CLOCK_IS_OFF 0x0
#define VO0_TCONLCD0_CLK_REG_VO0_TCONLCD0_CLK_GATING_CLOCK_IS_ON 0x1
#define VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0x000
#define VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0x001
#define VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X 0x010
#define VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X 0x011
#define VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_PERI0PLL2X 0x100
#define VO0_TCONLCD0_CLK_REG_FACTOR_M_OFFSET 0
#define VO0_TCONLCD0_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define VO0_TCONLCD1_CLK_REG 0x00000b64//VO0_TCONLCD1 Clock Register
#define VO0_TCONLCD1_CLK_REG_VO0_TCONLCD1_CLK_GATING_OFFSET 31
#define VO0_TCONLCD1_CLK_REG_VO0_TCONLCD1_CLK_GATING_CLEAR_MASK 0x80000000
#define VO0_TCONLCD1_CLK_REG_VO0_TCONLCD1_CLK_GATING_CLOCK_IS_OFF 0x0
#define VO0_TCONLCD1_CLK_REG_VO0_TCONLCD1_CLK_GATING_CLOCK_IS_ON 0x1
#define VO0_TCONLCD1_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define VO0_TCONLCD1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define VO0_TCONLCD1_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0x000
#define VO0_TCONLCD1_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0x001
#define VO0_TCONLCD1_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X 0x010
#define VO0_TCONLCD1_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X 0x011
#define VO0_TCONLCD1_CLK_REG_CLK_SRC_SEL_PERI0PLL2X 0x100
#define VO0_TCONLCD1_CLK_REG_FACTOR_M_OFFSET 0
#define VO0_TCONLCD1_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define VO1_TCONLCD0_CLK_REG 0x00000b68//VO1_TCONLCD0 Clock Register
#define VO1_TCONLCD0_CLK_REG_VO1_TCONLCD0_CLK_GATING_OFFSET 31
#define VO1_TCONLCD0_CLK_REG_VO1_TCONLCD0_CLK_GATING_CLEAR_MASK 0x80000000
#define VO1_TCONLCD0_CLK_REG_VO1_TCONLCD0_CLK_GATING_CLOCK_IS_OFF 0x0
#define VO1_TCONLCD0_CLK_REG_VO1_TCONLCD0_CLK_GATING_CLOCK_IS_ON 0x1
#define VO1_TCONLCD0_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define VO1_TCONLCD0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define VO1_TCONLCD0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0x000
#define VO1_TCONLCD0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0x001
#define VO1_TCONLCD0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X 0x010
#define VO1_TCONLCD0_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X 0x011
#define VO1_TCONLCD0_CLK_REG_CLK_SRC_SEL_PERI0PLL2X 0x100
#define VO1_TCONLCD0_CLK_REG_FACTOR_M_OFFSET 0
#define VO1_TCONLCD0_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define COMBPHY0_CLK_REG 0x00000b6c//COMBPHY0 Clock Register
#define COMBPHY0_CLK_REG_COMBPHY0_CLK_GATING_OFFSET 31
#define COMBPHY0_CLK_REG_COMBPHY0_CLK_GATING_CLEAR_MASK 0x80000000
#define COMBPHY0_CLK_REG_COMBPHY0_CLK_GATING_CLOCK_IS_OFF 0x0
#define COMBPHY0_CLK_REG_COMBPHY0_CLK_GATING_CLOCK_IS_ON 0x1
#define COMBPHY0_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define COMBPHY0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define COMBPHY0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0x000
#define COMBPHY0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0x001
#define COMBPHY0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X 0x010
#define COMBPHY0_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X 0x011
#define COMBPHY0_CLK_REG_CLK_SRC_SEL_PERI0PLL2X 0x100
#define COMBPHY0_CLK_REG_FACTOR_M_OFFSET 0
#define COMBPHY0_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define COMBPHY1_CLK_REG 0x00000b70//COMBPHY1 Clock Register
#define COMBPHY1_CLK_REG_COMBPHY1_CLK_GATING_OFFSET 31
#define COMBPHY1_CLK_REG_COMBPHY1_CLK_GATING_CLEAR_MASK 0x80000000
#define COMBPHY1_CLK_REG_COMBPHY1_CLK_GATING_CLOCK_IS_OFF 0x0
#define COMBPHY1_CLK_REG_COMBPHY1_CLK_GATING_CLOCK_IS_ON 0x1
#define COMBPHY1_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define COMBPHY1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define COMBPHY1_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0x000
#define COMBPHY1_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0x001
#define COMBPHY1_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X 0x010
#define COMBPHY1_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X 0x011
#define COMBPHY1_CLK_REG_CLK_SRC_SEL_PERI0PLL2X 0x100
#define COMBPHY1_CLK_REG_FACTOR_M_OFFSET 0
#define COMBPHY1_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define TCONLCD_BGR_REG 0x00000b7c//TCONLCD Bus Gating Reset Register
#define TCONLCD_BGR_REG_VO1_TCONLCD0_RST_OFFSET 18
#define TCONLCD_BGR_REG_VO1_TCONLCD0_RST_CLEAR_MASK 0x00040000
#define TCONLCD_BGR_REG_VO1_TCONLCD0_RST_ASSERT 0x0
#define TCONLCD_BGR_REG_VO1_TCONLCD0_RST_DE_ASSERT 0x1
#define TCONLCD_BGR_REG_VO0_TCONLCD1_RST_OFFSET 17
#define TCONLCD_BGR_REG_VO0_TCONLCD1_RST_CLEAR_MASK 0x00020000
#define TCONLCD_BGR_REG_VO0_TCONLCD1_RST_ASSERT 0x0
#define TCONLCD_BGR_REG_VO0_TCONLCD1_RST_DE_ASSERT 0x1
#define TCONLCD_BGR_REG_VO0_TCONLCD0_RST_OFFSET 16
#define TCONLCD_BGR_REG_VO0_TCONLCD0_RST_CLEAR_MASK 0x00010000
#define TCONLCD_BGR_REG_VO0_TCONLCD0_RST_ASSERT 0x0
#define TCONLCD_BGR_REG_VO0_TCONLCD0_RST_DE_ASSERT 0x1
#define TCONLCD_BGR_REG_VO1_TCONLCD0_GATING_OFFSET 2
#define TCONLCD_BGR_REG_VO1_TCONLCD0_GATING_CLEAR_MASK 0x00000004
#define TCONLCD_BGR_REG_VO1_TCONLCD0_GATING_MASK 0x0
#define TCONLCD_BGR_REG_VO1_TCONLCD0_GATING_PASS 0x1
#define TCONLCD_BGR_REG_VO0_TCONLCD1_GATING_OFFSET 1
#define TCONLCD_BGR_REG_VO0_TCONLCD1_GATING_CLEAR_MASK 0x00000002
#define TCONLCD_BGR_REG_VO0_TCONLCD1_GATING_MASK 0x0
#define TCONLCD_BGR_REG_VO0_TCONLCD1_GATING_PASS 0x1
#define TCONLCD_BGR_REG_VO0_TCONLCD0_GATING_OFFSET 0
#define TCONLCD_BGR_REG_VO0_TCONLCD0_GATING_CLEAR_MASK 0x00000001
#define TCONLCD_BGR_REG_VO0_TCONLCD0_GATING_MASK 0x0
#define TCONLCD_BGR_REG_VO0_TCONLCD0_GATING_PASS 0x1

#define TCONTV_CLK_REG 0x00000b80//TCONTV Clock Register
#define TCONTV_CLK_REG_TCONTV_CLK_GATING_OFFSET 31
#define TCONTV_CLK_REG_TCONTV_CLK_GATING_CLEAR_MASK 0x80000000
#define TCONTV_CLK_REG_TCONTV_CLK_GATING_CLOCK_IS_OFF 0x0
#define TCONTV_CLK_REG_TCONTV_CLK_GATING_CLOCK_IS_ON 0x1
#define TCONTV_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define TCONTV_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define TCONTV_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0x000
#define TCONTV_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0x001
#define TCONTV_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X 0x010
#define TCONTV_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X 0x011
#define TCONTV_CLK_REG_CLK_SRC_SEL_PERI0PLL2X 0x100
#define TCONTV_CLK_REG_FACTOR_M_OFFSET 0
#define TCONTV_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define TCONTV_BGR_REG 0x00000b9c//TCONTV Bus Gating Reset Register
#define TCONTV_BGR_REG_TCONTV_RST_OFFSET 16
#define TCONTV_BGR_REG_TCONTV_RST_CLEAR_MASK 0x00010000
#define TCONTV_BGR_REG_TCONTV_RST_ASSERT 0x0
#define TCONTV_BGR_REG_TCONTV_RST_DE_ASSERT 0x1
#define TCONTV_BGR_REG_TCONTV_GATING_OFFSET 0
#define TCONTV_BGR_REG_TCONTV_GATING_CLEAR_MASK 0x00000001
#define TCONTV_BGR_REG_TCONTV_GATING_MASK 0x0
#define TCONTV_BGR_REG_TCONTV_GATING_PASS 0x1

#define LVDS_BGR_REG 0x00000bac//LVDS Bus Gating Reset Register
#define LVDS_BGR_REG_LVDS1_RST_OFFSET 17
#define LVDS_BGR_REG_LVDS1_RST_CLEAR_MASK 0x00020000
#define LVDS_BGR_REG_LVDS1_RST_ASSERT 0x0
#define LVDS_BGR_REG_LVDS1_RST_DE_ASSERT 0x1
#define LVDS_BGR_REG_LVDS0_RST_OFFSET 16
#define LVDS_BGR_REG_LVDS0_RST_CLEAR_MASK 0x00010000
#define LVDS_BGR_REG_LVDS0_RST_ASSERT 0x0
#define LVDS_BGR_REG_LVDS0_RST_DE_ASSERT 0x1

#define LEDC_CLK_REG 0x00000bf0//LEDC Clock Register
#define LEDC_CLK_REG_LEDC_CLK_GATING_OFFSET 31
#define LEDC_CLK_REG_LEDC_CLK_GATING_CLEAR_MASK 0x80000000
#define LEDC_CLK_REG_LEDC_CLK_GATING_CLOCK_IS_OFF 0x0
#define LEDC_CLK_REG_LEDC_CLK_GATING_CLOCK_IS_ON 0x1
#define LEDC_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define LEDC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x01000000
#define LEDC_CLK_REG_CLK_SRC_SEL_HOSC 0x000
#define LEDC_CLK_REG_CLK_SRC_SEL_PERI0_600M 0x001
#define LEDC_CLK_REG_FACTOR_M_OFFSET 0
#define LEDC_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define LEDC_BGR_REG 0x00000bfc//LEDC Bus Gating Reset Register
#define LEDC_BGR_REG_LEDC_RST_OFFSET 16
#define LEDC_BGR_REG_LEDC_RST_CLEAR_MASK 0x00010000
#define LEDC_BGR_REG_LEDC_RST_ASSERT 0x0
#define LEDC_BGR_REG_LEDC_RST_DE_ASSERT 0x1
#define LEDC_BGR_REG_LEDC_GATING_OFFSET 0
#define LEDC_BGR_REG_LEDC_GATING_CLEAR_MASK 0x00000001
#define LEDC_BGR_REG_LEDC_GATING_MASK 0x0
#define LEDC_BGR_REG_LEDC_GATING_PASS 0x1

#define CSI_CLK_REG 0x00000c04//CSI Clock Register
#define CSI_CLK_REG_CSI_CLK_GATING_OFFSET 31
#define CSI_CLK_REG_CSI_CLK_GATING_CLEAR_MASK 0x80000000
#define CSI_CLK_REG_CSI_CLK_GATING_CLOCK_IS_OFF 0x0
#define CSI_CLK_REG_CSI_CLK_GATING_CLOCK_IS_ON 0x1
#define CSI_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define CSI_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define CSI_CLK_REG_CLK_SRC_SEL_PERI0_300M 0x000
#define CSI_CLK_REG_CLK_SRC_SEL_PERI0_400M 0x001
#define CSI_CLK_REG_CLK_SRC_SEL_PERI0_480M 0x010
#define CSI_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0x011
#define CSI_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X 0x100
#define CSI_CLK_REG_FACTOR_M_OFFSET 0
#define CSI_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define CSI_MASTER0_CLK_REG 0x00000c08//CSI Master0 Clock Register
#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_OFFSET 31
#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_CLEAR_MASK 0x80000000
#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_CLOCK_IS_OFF 0x0
#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_CLOCK_IS_ON 0x1
#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_HOSC 0x000
#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X 0x001
#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0x010
#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0x011
#define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X 0x100
#define CSI_MASTER0_CLK_REG_FACTOR_N_OFFSET 8
#define CSI_MASTER0_CLK_REG_FACTOR_N_CLEAR_MASK 0x00001f00
#define CSI_MASTER0_CLK_REG_FACTOR_M_OFFSET 0
#define CSI_MASTER0_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define CSI_MASTER1_CLK_REG 0x00000c0c//CSI Master1 Clock Register
#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_OFFSET 31
#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_CLEAR_MASK 0x80000000
#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_CLOCK_IS_OFF 0x0
#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_CLOCK_IS_ON 0x1
#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_HOSC 0x000
#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X 0x001
#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0x010
#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0x011
#define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X 0x100
#define CSI_MASTER1_CLK_REG_FACTOR_N_OFFSET 8
#define CSI_MASTER1_CLK_REG_FACTOR_N_CLEAR_MASK 0x00001f00
#define CSI_MASTER1_CLK_REG_FACTOR_M_OFFSET 0
#define CSI_MASTER1_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define CSI_MASTER2_CLK_REG 0x00000c10//CSI Master2 Clock Register
#define CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_OFFSET 31
#define CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_CLEAR_MASK 0x80000000
#define CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_CLOCK_IS_OFF 0x0
#define CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_CLOCK_IS_ON 0x1
#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_HOSC 0x000
#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X 0x001
#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0x010
#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0x011
#define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X 0x100
#define CSI_MASTER2_CLK_REG_FACTOR_N_OFFSET 8
#define CSI_MASTER2_CLK_REG_FACTOR_N_CLEAR_MASK 0x00001f00
#define CSI_MASTER2_CLK_REG_FACTOR_M_OFFSET 0
#define CSI_MASTER2_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define CSI_MASTER3_CLK_REG 0x00000c14//CSI Master3 Clock Register
#define CSI_MASTER3_CLK_REG_CSI_MASTER3_CLK_GATING_OFFSET 31
#define CSI_MASTER3_CLK_REG_CSI_MASTER3_CLK_GATING_CLEAR_MASK 0x80000000
#define CSI_MASTER3_CLK_REG_CSI_MASTER3_CLK_GATING_CLOCK_IS_OFF 0x0
#define CSI_MASTER3_CLK_REG_CSI_MASTER3_CLK_GATING_CLOCK_IS_ON 0x1
#define CSI_MASTER3_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define CSI_MASTER3_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define CSI_MASTER3_CLK_REG_CLK_SRC_SEL_HOSC 0x000
#define CSI_MASTER3_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X 0x001
#define CSI_MASTER3_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0x010
#define CSI_MASTER3_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0x011
#define CSI_MASTER3_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X 0x100
#define CSI_MASTER3_CLK_REG_FACTOR_N_OFFSET 8
#define CSI_MASTER3_CLK_REG_FACTOR_N_CLEAR_MASK 0x00001f00
#define CSI_MASTER3_CLK_REG_FACTOR_M_OFFSET 0
#define CSI_MASTER3_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define CSI_BGR_REG 0x00000c1c//CSI Bus Gating Reset Register
#define CSI_BGR_REG_CSI_RST_OFFSET 16
#define CSI_BGR_REG_CSI_RST_CLEAR_MASK 0x00010000
#define CSI_BGR_REG_CSI_RST_ASSERT 0x0
#define CSI_BGR_REG_CSI_RST_DE_ASSERT 0x1
#define CSI_BGR_REG_CSI_GATING_OFFSET 0
#define CSI_BGR_REG_CSI_GATING_CLEAR_MASK 0x00000001
#define CSI_BGR_REG_CSI_GATING_MASK 0x0
#define CSI_BGR_REG_CSI_GATING_PASS 0x1

#define ISP_CLK_REG 0x00000c20//ISP Clock Register
#define ISP_CLK_REG_ISP_CLK_GATING_OFFSET 31
#define ISP_CLK_REG_ISP_CLK_GATING_CLEAR_MASK 0x80000000
#define ISP_CLK_REG_ISP_CLK_GATING_CLOCK_IS_OFF 0x0
#define ISP_CLK_REG_ISP_CLK_GATING_CLOCK_IS_ON 0x1
#define ISP_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define ISP_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define ISP_CLK_REG_CLK_SRC_SEL_PERI0_300M 0x000
#define ISP_CLK_REG_CLK_SRC_SEL_PERI0_400M 0x001
#define ISP_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0x010
#define ISP_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X 0x011
#define ISP_CLK_REG_FACTOR_M_OFFSET 0
#define ISP_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define ISP_BGR_REG 0x00000c2c//ISP Bus Gating Reset Register
#define ISP_BGR_REG_ISP_RST_OFFSET 16
#define ISP_BGR_REG_ISP_RST_CLEAR_MASK 0x00010000
#define ISP_BGR_REG_ISP_RST_ASSERT 0x0
#define ISP_BGR_REG_ISP_RST_DE_ASSERT 0x1

#define DSP_CLK_REG 0x00000c70//DSP Clock Register
#define DSP_CLK_REG_DSP_CLK_GATING_OFFSET 31
#define DSP_CLK_REG_DSP_CLK_GATING_CLEAR_MASK 0x80000000
#define DSP_CLK_REG_DSP_CLK_GATING_CLOCK_IS_OFF 0x0
#define DSP_CLK_REG_DSP_CLK_GATING_CLOCK_IS_ON 0x1
#define DSP_CLK_REG_CLK_SRC_SEL_OFFSET 24
#define DSP_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
#define DSP_CLK_REG_CLK_SRC_SEL_HOSC 0x000
#define DSP_CLK_REG_CLK_SRC_SEL_CLK32K 0x001
#define DSP_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0x010
#define DSP_CLK_REG_CLK_SRC_SEL_PERI0PLL2X 0x011
#define DSP_CLK_REG_CLK_SRC_SEL_PERI0_480M 0x100
#define DSP_CLK_REG_FACTOR_M_OFFSET 0
#define DSP_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define AHB_GATE_EN_REG 0x00000e04//AHB Gate Enable Register
#define AHB_GATE_EN_REG_AHB_MONITOR_EN_OFFSET 31
#define AHB_GATE_EN_REG_AHB_MONITOR_EN_CLEAR_MASK 0x80000000
#define AHB_GATE_EN_REG_AHB_MONITOR_EN_DISABLE_AUTO_CLOCK_GATE 0x0
#define AHB_GATE_EN_REG_AHB_MONITOR_EN_ENABLE_AUTO_CLOCK_GATE 0x1
#define AHB_GATE_EN_REG_SD_MONITOR_EN_OFFSET 29
#define AHB_GATE_EN_REG_SD_MONITOR_EN_CLEAR_MASK 0x20000000
#define AHB_GATE_EN_REG_SD_MONITOR_EN_DISABLE_AUTO_CLOCK_GATE 0x0
#define AHB_GATE_EN_REG_SD_MONITOR_EN_ENABLE_AUTO_CLOCK_GATE 0x1
#define AHB_GATE_EN_REG_CPUS_HCLK_GATE_SW_CFG_OFFSET 28
#define AHB_GATE_EN_REG_CPUS_HCLK_GATE_SW_CFG_CLEAR_MASK 0x10000000
#define AHB_GATE_EN_REG_CPUS_HCLK_GATE_SW_CFG_DISABLE 0x0
#define AHB_GATE_EN_REG_CPUS_HCLK_GATE_SW_CFG_ENABLE 0x1
#define AHB_GATE_EN_REG_SPIF_MBUS_AHB_GATE_SW_CFG_OFFSET 22
#define AHB_GATE_EN_REG_SPIF_MBUS_AHB_GATE_SW_CFG_CLEAR_MASK 0x00400000
#define AHB_GATE_EN_REG_SPIF_MBUS_AHB_GATE_SW_CFG_DISABLE 0x0
#define AHB_GATE_EN_REG_SPIF_MBUS_AHB_GATE_SW_CFG_ENABLE 0x1
#define AHB_GATE_EN_REG_GMAC1_MBUS_AHB_GATE_SW_CFG_OFFSET 21
#define AHB_GATE_EN_REG_GMAC1_MBUS_AHB_GATE_SW_CFG_CLEAR_MASK 0x00200000
#define AHB_GATE_EN_REG_GMAC1_MBUS_AHB_GATE_SW_CFG_DISABLE 0x0
#define AHB_GATE_EN_REG_GMAC1_MBUS_AHB_GATE_SW_CFG_ENABLE 0x1
#define AHB_GATE_EN_REG_GMAC0_MBUS_AHB_GATE_SW_CFG_OFFSET 20
#define AHB_GATE_EN_REG_GMAC0_MBUS_AHB_GATE_SW_CFG_CLEAR_MASK 0x00100000
#define AHB_GATE_EN_REG_GMAC0_MBUS_AHB_GATE_SW_CFG_DISABLE 0x0
#define AHB_GATE_EN_REG_GMAC0_MBUS_AHB_GATE_SW_CFG_ENABLE 0x1
#define AHB_GATE_EN_REG_SMHC2_MBUS_AHB_GATE_SW_CFG_OFFSET 19
#define AHB_GATE_EN_REG_SMHC2_MBUS_AHB_GATE_SW_CFG_CLEAR_MASK 0x00080000
#define AHB_GATE_EN_REG_SMHC2_MBUS_AHB_GATE_SW_CFG_DISABLE 0x0
#define AHB_GATE_EN_REG_SMHC2_MBUS_AHB_GATE_SW_CFG_ENABLE 0x1
#define AHB_GATE_EN_REG_SMHC1_MBUS_AHB_GATE_SW_CFG_OFFSET 18
#define AHB_GATE_EN_REG_SMHC1_MBUS_AHB_GATE_SW_CFG_CLEAR_MASK 0x00040000
#define AHB_GATE_EN_REG_SMHC1_MBUS_AHB_GATE_SW_CFG_DISABLE 0x0
#define AHB_GATE_EN_REG_SMHC1_MBUS_AHB_GATE_SW_CFG_ENABLE 0x1
#define AHB_GATE_EN_REG_SMHC0_MBUS_AHB_GATE_SW_CFG_OFFSET 17
#define AHB_GATE_EN_REG_SMHC0_MBUS_AHB_GATE_SW_CFG_CLEAR_MASK 0x00020000
#define AHB_GATE_EN_REG_SMHC0_MBUS_AHB_GATE_SW_CFG_DISABLE 0x0
#define AHB_GATE_EN_REG_SMHC0_MBUS_AHB_GATE_SW_CFG_ENABLE 0x1
#define AHB_GATE_EN_REG_USB_MBUS_AHB_GATE_SW_CFG_OFFSET 16
#define AHB_GATE_EN_REG_USB_MBUS_AHB_GATE_SW_CFG_CLEAR_MASK 0x00010000
#define AHB_GATE_EN_REG_USB_MBUS_AHB_GATE_SW_CFG_DISABLE 0x0
#define AHB_GATE_EN_REG_USB_MBUS_AHB_GATE_SW_CFG_ENABLE 0x1
#define AHB_GATE_EN_REG_GMAC1_AHB_GATE_SW_CFG_OFFSET 9
#define AHB_GATE_EN_REG_GMAC1_AHB_GATE_SW_CFG_CLEAR_MASK 0x00000200
#define AHB_GATE_EN_REG_GMAC1_AHB_GATE_SW_CFG_DISABLE 0x0
#define AHB_GATE_EN_REG_GMAC1_AHB_GATE_SW_CFG_ENABLE 0x1
#define AHB_GATE_EN_REG_GMAC0_AHB_GATE_SW_CFG_OFFSET 8
#define AHB_GATE_EN_REG_GMAC0_AHB_GATE_SW_CFG_CLEAR_MASK 0x00000100
#define AHB_GATE_EN_REG_GMAC0_AHB_GATE_SW_CFG_DISABLE 0x0
#define AHB_GATE_EN_REG_GMAC0_AHB_GATE_SW_CFG_ENABLE 0x1
#define AHB_GATE_EN_REG_SMHC2_AHB_GATE_SW_CFG_OFFSET 7
#define AHB_GATE_EN_REG_SMHC2_AHB_GATE_SW_CFG_CLEAR_MASK 0x00000080
#define AHB_GATE_EN_REG_SMHC2_AHB_GATE_SW_CFG_DISABLE 0x0
#define AHB_GATE_EN_REG_SMHC2_AHB_GATE_SW_CFG_ENABLE 0x1
#define AHB_GATE_EN_REG_SMHC1_AHB_GATE_SW_CFG_OFFSET 6
#define AHB_GATE_EN_REG_SMHC1_AHB_GATE_SW_CFG_CLEAR_MASK 0x00000040
#define AHB_GATE_EN_REG_SMHC1_AHB_GATE_SW_CFG_DISABLE 0x0
#define AHB_GATE_EN_REG_SMHC1_AHB_GATE_SW_CFG_ENABLE 0x1
#define AHB_GATE_EN_REG_SMHC0_AHB_GATE_SW_CFG_OFFSET 5
#define AHB_GATE_EN_REG_SMHC0_AHB_GATE_SW_CFG_CLEAR_MASK 0x00000020
#define AHB_GATE_EN_REG_SMHC0_AHB_GATE_SW_CFG_DISABLE 0x0
#define AHB_GATE_EN_REG_SMHC0_AHB_GATE_SW_CFG_ENABLE 0x1
#define AHB_GATE_EN_REG_USB_AHB_GATE_SW_CFG_OFFSET 4
#define AHB_GATE_EN_REG_USB_AHB_GATE_SW_CFG_CLEAR_MASK 0x00000010
#define AHB_GATE_EN_REG_USB_AHB_GATE_SW_CFG_DISABLE 0x0
#define AHB_GATE_EN_REG_USB_AHB_GATE_SW_CFG_ENABLE 0x1
#define AHB_GATE_EN_REG_VID_OUT_AHB_GATE_SW_CFG_OFFSET 3
#define AHB_GATE_EN_REG_VID_OUT_AHB_GATE_SW_CFG_CLEAR_MASK 0x00000008
#define AHB_GATE_EN_REG_VID_OUT_AHB_GATE_SW_CFG_DISABLE 0x0
#define AHB_GATE_EN_REG_VID_OUT_AHB_GATE_SW_CFG_ENABLE 0x1
#define AHB_GATE_EN_REG_VID_IN_AHB_GATE_SW_CFG_OFFSET 2
#define AHB_GATE_EN_REG_VID_IN_AHB_GATE_SW_CFG_CLEAR_MASK 0x00000004
#define AHB_GATE_EN_REG_VID_IN_AHB_GATE_SW_CFG_DISABLE 0x0
#define AHB_GATE_EN_REG_VID_IN_AHB_GATE_SW_CFG_ENABLE 0x1
#define AHB_GATE_EN_REG_VE_AHB_GATE_SW_CFG_OFFSET 1
#define AHB_GATE_EN_REG_VE_AHB_GATE_SW_CFG_CLEAR_MASK 0x00000002
#define AHB_GATE_EN_REG_VE_AHB_GATE_SW_CFG_DISABLE 0x0
#define AHB_GATE_EN_REG_VE_AHB_GATE_SW_CFG_ENABLE 0x1
#define AHB_GATE_EN_REG_NPU_AHB_GATE_SW_CFG_OFFSET 0
#define AHB_GATE_EN_REG_NPU_AHB_GATE_SW_CFG_CLEAR_MASK 0x00000001
#define AHB_GATE_EN_REG_NPU_AHB_GATE_SW_CFG_DISABLE 0x0
#define AHB_GATE_EN_REG_NPU_AHB_GATE_SW_CFG_ENABLE 0x1

#define PERI0PLL_GATE_EN_REG 0x00000e08//PERI0PLL Gate Enable Register
#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_OFFSET 27
#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_CLEAR_MASK 0x08000000
#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_DISABLE 0x0
#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_ENABLE 0x1
#define PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_OFFSET 26
#define PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_CLEAR_MASK 0x04000000
#define PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_DISABLE 0x0
#define PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_ENABLE 0x1
#define PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_OFFSET 25
#define PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_CLEAR_MASK 0x02000000
#define PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_DISABLE 0x0
#define PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_ENABLE 0x1
#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_OFFSET 24
#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_CLEAR_MASK 0x01000000
#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_DISABLE 0x0
#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_ENABLE 0x1
#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_OFFSET 23
#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_CLEAR_MASK 0x00800000
#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_DISABLE 0x0
#define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_ENABLE 0x1
#define PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_OFFSET 22
#define PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_CLEAR_MASK 0x00400000
#define PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_DISABLE 0x0
#define PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_ENABLE 0x1
#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_OFFSET 21
#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_CLEAR_MASK 0x00200000
#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_DISABLE 0x0
#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_ENABLE 0x1
#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_OFFSET 20
#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_CLEAR_MASK 0x00100000
#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_DISABLE 0x0
#define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_ENABLE 0x1
#define PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_OFFSET 19
#define PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_CLEAR_MASK 0x00080000
#define PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_DISABLE 0x0
#define PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_ENABLE 0x1
#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_OFFSET 18
#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_CLEAR_MASK 0x00040000
#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_DISABLE 0x0
#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_ENABLE 0x1
#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_OFFSET 17
#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_CLEAR_MASK 0x00020000
#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_DISABLE 0x0
#define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_ENABLE 0x1
#define PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_OFFSET 16
#define PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_CLEAR_MASK 0x00010000
#define PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_DISABLE 0x0
#define PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_ENABLE 0x1
#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_OFFSET 11
#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_CLEAR_MASK 0x00000800
#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_AUTO 0x0
#define PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_NO_AUTO 0x1
#define PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_OFFSET 10
#define PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_CLEAR_MASK 0x00000400
#define PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_AUTO 0x0
#define PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_NO_AUTO 0x1
#define PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_OFFSET 9
#define PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_CLEAR_MASK 0x00000200
#define PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_AUTO 0x0
#define PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_NO_AUTO 0x1
#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_OFFSET 8
#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_CLEAR_MASK 0x00000100
#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_AUTO 0x0
#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_NO_AUTO 0x1
#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_OFFSET 7
#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_CLEAR_MASK 0x00000080
#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_AUTO 0x0
#define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_NO_AUTO 0x1
#define PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_OFFSET 6
#define PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_CLEAR_MASK 0x00000040
#define PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_AUTO 0x0
#define PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_NO_AUTO 0x1
#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_OFFSET 5
#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_CLEAR_MASK 0x00000020
#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_AUTO 0x0
#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_NO_AUTO 0x1
#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_OFFSET 4
#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_CLEAR_MASK 0x00000010
#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_AUTO 0x0
#define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_NO_AUTO 0x1
#define PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_OFFSET 3
#define PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_CLEAR_MASK 0x00000008
#define PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_AUTO 0x0
#define PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_NO_AUTO 0x1
#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_OFFSET 2
#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_CLEAR_MASK 0x00000004
#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_AUTO 0x0
#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_NO_AUTO 0x1
#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_OFFSET 1
#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_CLEAR_MASK 0x00000002
#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_AUTO 0x0
#define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_NO_AUTO 0x1
#define PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_OFFSET 0
#define PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_CLEAR_MASK 0x00000001
#define PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_AUTO 0x0
#define PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_NO_AUTO 0x1

#define CLK24M_GATE_EN_REG 0x00000e0c//CLK24M Gate Enable Register
#define CLK24M_GATE_EN_REG_RES_DCAP_24M_GATE_EN_OFFSET 3
#define CLK24M_GATE_EN_REG_RES_DCAP_24M_GATE_EN_CLEAR_MASK 0x00000008
#define CLK24M_GATE_EN_REG_RES_DCAP_24M_GATE_EN_DISABLE 0x0
#define CLK24M_GATE_EN_REG_RES_DCAP_24M_GATE_EN_ENABLE 0x1
#define CLK24M_GATE_EN_REG_WIEGAND_24M_GATE_EN_OFFSET 1
#define CLK24M_GATE_EN_REG_WIEGAND_24M_GATE_EN_CLEAR_MASK 0x00000002
#define CLK24M_GATE_EN_REG_WIEGAND_24M_GATE_EN_DISABLE 0x0
#define CLK24M_GATE_EN_REG_WIEGAND_24M_GATE_EN_ENABLE 0x1
#define CLK24M_GATE_EN_REG_USB_24M_GATE_EN_OFFSET 0
#define CLK24M_GATE_EN_REG_USB_24M_GATE_EN_CLEAR_MASK 0x00000001
#define CLK24M_GATE_EN_REG_USB_24M_GATE_EN_DISABLE 0x0
#define CLK24M_GATE_EN_REG_USB_24M_GATE_EN_ENABLE 0x1

#define CCU_SEC_SWITCH_REG 0x00000f00//CCU Security Switch Register
#define CCU_SEC_SWITCH_REG_MBUS_SEC_OFFSET 2
#define CCU_SEC_SWITCH_REG_MBUS_SEC_CLEAR_MASK 0x00000004
#define CCU_SEC_SWITCH_REG_MBUS_SEC_SECURE 0x0
#define CCU_SEC_SWITCH_REG_MBUS_SEC_NON_SECURE 0x1
#define CCU_SEC_SWITCH_REG_BUS_SEC_OFFSET 1
#define CCU_SEC_SWITCH_REG_BUS_SEC_CLEAR_MASK 0x00000002
#define CCU_SEC_SWITCH_REG_BUS_SEC_SECURE 0x0
#define CCU_SEC_SWITCH_REG_BUS_SEC_NON_SECURE 0x1
#define CCU_SEC_SWITCH_REG_PLL_SEC_OFFSET 0
#define CCU_SEC_SWITCH_REG_PLL_SEC_CLEAR_MASK 0x00000001
#define CCU_SEC_SWITCH_REG_PLL_SEC_SECURE 0x0
#define CCU_SEC_SWITCH_REG_PLL_SEC_NON_SECURE 0x1

#define PLL_LOCK_DBG_CTRL_REG 0x00000f04//PLL Lock Debug Control Register
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_OFFSET 31
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_CLEAR_MASK 0x80000000
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_DISABLE 0x0
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_ENABLE 0x1
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_OFFSET 20
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_CLEAR_MASK 0x00700000
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_CPUPLL 0x000
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_DDRPLL 0x001
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_PERIPLL2X 0x010
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_VIDEO0PLL4X 0x011
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_CSIPLL4X 0x100
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_AUDIOPLL4X 0x110
#define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_NPUPLL 0x111

#define SYSDAP_REQ_CTRL_REG 0x00000f08//SYSDAP REQ Control Register
#define SYSDAP_REQ_CTRL_REG_SYSDAP_REQ_ENABLE_OFFSET 0
#define SYSDAP_REQ_CTRL_REG_SYSDAP_REQ_ENABLE_CLEAR_MASK 0x00000001

#define CCU_FAN_GATE_REG 0x00000f30//CCU FANOUT CLOCK GATE Register
#define CCU_FAN_GATE_REG_CLK25M_EN_OFFSET 3
#define CCU_FAN_GATE_REG_CLK25M_EN_CLEAR_MASK 0x00000008
#define CCU_FAN_GATE_REG_CLK25M_EN_CLOCK_IS_OFF 0x0
#define CCU_FAN_GATE_REG_CLK25M_EN_CLOCK_IS_ON 0x1
#define CCU_FAN_GATE_REG_CLK16M_EN_OFFSET 2
#define CCU_FAN_GATE_REG_CLK16M_EN_CLEAR_MASK 0x00000004
#define CCU_FAN_GATE_REG_CLK16M_EN_CLOCK_IS_OFF 0x0
#define CCU_FAN_GATE_REG_CLK16M_EN_CLOCK_IS_ON 0x1
#define CCU_FAN_GATE_REG_CLK12M_EN_OFFSET 1
#define CCU_FAN_GATE_REG_CLK12M_EN_CLEAR_MASK 0x00000002
#define CCU_FAN_GATE_REG_CLK12M_EN_CLOCK_IS_OFF 0x0
#define CCU_FAN_GATE_REG_CLK12M_EN_CLOCK_IS_ON 0x1
#define CCU_FAN_GATE_REG_CLK24M_EN_OFFSET 0
#define CCU_FAN_GATE_REG_CLK24M_EN_CLEAR_MASK 0x00000001
#define CCU_FAN_GATE_REG_CLK24M_EN_CLOCK_IS_OFF 0x0
#define CCU_FAN_GATE_REG_CLK24M_EN_CLOCK_IS_ON 0x1

#define CLK27M_FAN_REG 0x00000f34//CLK27M FANOUT Register
#define CLK27M_FAN_REG_CLK27M_EN_OFFSET 31
#define CLK27M_FAN_REG_CLK27M_EN_CLEAR_MASK 0x80000000
#define CLK27M_FAN_REG_CLK27M_EN_CLOCK_IS_OFF 0x0
#define CLK27M_FAN_REG_CLK27M_EN_CLOCK_IS_ON 0x1
#define CLK27M_FAN_REG_CLK27M_SCR_SEL_OFFSET 24
#define CLK27M_FAN_REG_CLK27M_SCR_SEL_CLEAR_MASK 0x03000000
#define CLK27M_FAN_REG_CLK27M_SCR_SEL_VIDEO0PLL1X 0x000
#define CLK27M_FAN_REG_CLK27M_SCR_SEL_VIDEO1PLL1X 0x001
#define CLK27M_FAN_REG_CLK27M_SCR_SEL_VIDEO2PLL1X 0x010
#define CLK27M_FAN_REG_CLK27M_SCR_SEL_VIDEO3PLL1X 0x011
#define CLK27M_FAN_REG_CLK27M_DIV1_OFFSET 8
#define CLK27M_FAN_REG_CLK27M_DIV1_CLEAR_MASK 0x00001f00
#define CLK27M_FAN_REG_CLK27M_DIV0_OFFSET 0
#define CLK27M_FAN_REG_CLK27M_DIV0_CLEAR_MASK 0x0000001f

#define CLK_FAN_REG 0x00000f38//CLK FANOUT Register
#define CLK_FAN_REG_PCLK_DIV_EN_OFFSET 31
#define CLK_FAN_REG_PCLK_DIV_EN_CLEAR_MASK 0x80000000
#define CLK_FAN_REG_PCLK_DIV_EN_CLOCK_IS_OFF 0x0
#define CLK_FAN_REG_PCLK_DIV_EN_CLOCK_IS_ON 0x1
#define CLK_FAN_REG_PCLK_DIV1_OFFSET 5
#define CLK_FAN_REG_PCLK_DIV1_CLEAR_MASK 0x000003e0
#define CLK_FAN_REG_PCLK_DIV_OFFSET 0
#define CLK_FAN_REG_PCLK_DIV_CLEAR_MASK 0x0000001f

#define CCU_FAN_REG 0x00000f3c//CCU FANOUT Register
#define CCU_FAN_REG_CLK_FANOUT2_EN_OFFSET 23
#define CCU_FAN_REG_CLK_FANOUT2_EN_CLEAR_MASK 0x00800000
#define CCU_FAN_REG_CLK_FANOUT2_EN_CLOCK_IS_OFF 0x0
#define CCU_FAN_REG_CLK_FANOUT2_EN_CLOCK_IS_ON 0x1
#define CCU_FAN_REG_CLK_FANOUT1_EN_OFFSET 22
#define CCU_FAN_REG_CLK_FANOUT1_EN_CLEAR_MASK 0x00400000
#define CCU_FAN_REG_CLK_FANOUT1_EN_CLOCK_IS_OFF 0x0
#define CCU_FAN_REG_CLK_FANOUT1_EN_CLOCK_IS_ON 0x1
#define CCU_FAN_REG_CLK_FANOUT0_EN_OFFSET 21
#define CCU_FAN_REG_CLK_FANOUT0_EN_CLEAR_MASK 0x00200000
#define CCU_FAN_REG_CLK_FANOUT0_EN_CLOCK_IS_OFF 0x0
#define CCU_FAN_REG_CLK_FANOUT0_EN_CLOCK_IS_ON 0x1
#define CCU_FAN_REG_CLK_FANOUT2_SEL_OFFSET 6
#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLEAR_MASK 0x000001c0
#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLK32K_FANOUT_FROM_SYSRTC 0x000
#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLK12M_FROM_DCXO_2 0x001
#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLK16M_FROM_PERI_160M_10 0x010
#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLK24M_FROM_DCXO 0x011
#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLK25M_FROM_PERI_150M_6 0x100
#define CCU_FAN_REG_CLK_FANOUT2_SEL_CLK27M 0x101
#define CCU_FAN_REG_CLK_FANOUT2_SEL_PCLK 0x110
#define CCU_FAN_REG_CLK_FANOUT1_SEL_OFFSET 3
#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLEAR_MASK 0x00000038
#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLK32K_FANOUT_FROM_SYSRTC 0x000
#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLK12M_FROM_DCXO_2 0x001
#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLK16M_FROM_PERI_160M_10 0x010
#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLK24M_FROM_DCXO 0x011
#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLK25M_FROM_PERI_150M_6 0x100
#define CCU_FAN_REG_CLK_FANOUT1_SEL_CLK27M 0x101
#define CCU_FAN_REG_CLK_FANOUT1_SEL_PCLK 0x110
#define CCU_FAN_REG_CLK_FANOUT0_SEL_OFFSET 0
#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLEAR_MASK 0x00000007
#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLK32K_FANOUT_FROM_SYSRTC 0x000
#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLK12M_FROM_DCXO_2 0x001
#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLK16M_FROM_PERI_160M_10 0x010
#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLK24M_FROM_DCXO 0x011
#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLK25M_FROM_PERI_150M_6 0x100
#define CCU_FAN_REG_CLK_FANOUT0_SEL_CLK27M 0x101
#define CCU_FAN_REG_CLK_FANOUT0_SEL_PCLK 0x110

#define PLL_CFG0_REG 0x00000f40//PLL Configuration0 Register
#define PLL_CFG0_REG_PLL_CONFIG0_OFFSET 0
#define PLL_CFG0_REG_PLL_CONFIG0_CLEAR_MASK 0xffffffff

#define PLL_CFG1_REG 0x00000f44//PLL Configuration1 Register
#define PLL_CFG1_REG_PLL_CONFIG1_OFFSET 0
#define PLL_CFG1_REG_PLL_CONFIG1_CLEAR_MASK 0xffffffff

#define PLL_CFG2_REG 0x00000f48//PLL Configuration2 Register
#define PLL_CFG2_REG_PLL_CONFIG2_OFFSET 0
#define PLL_CFG2_REG_PLL_CONFIG2_CLEAR_MASK 0xffffffff

#define CCU_VERSION_REG 0x00000ff0//CCU Version Register
#define CCU_VERSION_REG_CCU_MAIN_VERSION_OFFSET 16
#define CCU_VERSION_REG_CCU_MAIN_VERSION_CLEAR_MASK 0xffff0000
#define CCU_VERSION_REG_CCU_SUB_VERSION_OFFSET 0
#define CCU_VERSION_REG_CCU_SUB_VERSION_CLEAR_MASK 0x0000ffff

#define CCU_BASE SUNXI_CCMU_BASE

#define APB2_CLK_SRC_OSC24M (APB1_CLK_REG_CLK_SRC_SEL_HOSC << APB1_CLK_REG_CLK_SRC_SEL_OFFSET)
#define APB2_CLK_SRC_OSC32K (APB2_CLK_SRC_OSC32K << APB1_CLK_REG_CLK_SRC_SEL_OFFSET)
#define APB2_CLK_SRC_PSI (APB1_CLK_REG_CLK_SRC_SEL_CLK16M_RC << APB1_CLK_REG_CLK_SRC_SEL_OFFSET)
#define APB2_CLK_SRC_PLL6 (APB1_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS << APB1_CLK_REG_CLK_SRC_SEL_OFFSET)

#define APB2_CLK_RATE_N_1 (0x0 << 8)
#define APB2_CLK_RATE_N_2 (0x1 << 8)
#define APB2_CLK_RATE_N_4 (0x2 << 8)
#define APB2_CLK_RATE_N_8 (0x3 << 8)
#define APB2_CLK_RATE_N_MASK (3 << 8)
#define APB2_CLK_RATE_M(m) (((m) -1) << APB1_CLK_REG_FACTOR_M_OFFSET)
#define APB2_CLK_RATE_M_MASK (3 << APB1_CLK_REG_FACTOR_M_OFFSET)

/* MMC clock bit field */
#define CCU_MMC_CTRL_M(x) ((x) -1)
#define CCU_MMC_CTRL_N(x) ((x) << SMHC0_CLK_REG_FACTOR_N_OFFSET)
#define CCU_MMC_CTRL_OSCM24 (SMHC0_CLK_REG_CLK_SRC_SEL_HOSC << SMHC0_CLK_REG_CLK_SRC_SEL_OFFSET)
#define CCU_MMC_CTRL_PLL6X2 (SMHC0_CLK_REG_CLK_SRC_SEL_PERI0_400M << SMHC0_CLK_REG_CLK_SRC_SEL_OFFSET)
#define CCU_MMC_CTRL_PLL_PERIPH2X2 (SMHC0_CLK_REG_CLK_SRC_SEL_PERI0_300M << SMHC0_CLK_REG_CLK_SRC_SEL_OFFSET)
#define CCU_MMC_CTRL_ENABLE (SMHC0_CLK_REG_SMHC0_CLK_GATING_CLOCK_IS_ON << SMHC0_CLK_REG_SMHC0_CLK_GATING_OFFSET)
/* if doesn't have these delays */
#define CCU_MMC_CTRL_OCLK_DLY(a) ((void) (a), 0)
#define CCU_MMC_CTRL_SCLK_DLY(a) ((void) (a), 0)

#define CCU_MMC_BGR_SMHC0_GATE (1 << 0)
#define CCU_MMC_BGR_SMHC1_GATE (1 << 1)
#define CCU_MMC_BGR_SMHC2_GATE (1 << 2)

#define CCU_MMC_BGR_SMHC0_RST (1 << 16)
#define CCU_MMC_BGR_SMHC1_RST (1 << 17)
#define CCU_MMC_BGR_SMHC2_RST (1 << 18)

/* Module gate/reset shift*/
#define RESET_SHIFT (16)
#define GATING_SHIFT (0)

/* pll list */
#define CCU_PLL_CPU0_CTRL_REG (SUNXI_CPU_SYS_CFG_BASE + 0x817000)
#define CCU_PLL_CPU1_CTRL_REG (SUNXI_CPU_SYS_CFG_BASE + 0x817000 + 0x04)
#define CCU_PLL_CPU2_CTRL_REG (SUNXI_CPU_SYS_CFG_BASE + 0x817000 + 0x08)
#define CCU_PLL_CPU3_CTRL_REG (SUNXI_CPU_SYS_CFG_BASE + 0x817000 + 0x0c)
#define CCU_PLL_DDR0_CTRL_REG (PLL_DDR_CTRL_REG)
#define CCU_PLL_DDR1_CTRL_REG (0x18)
#define CCU_PLL_PERI0_CTRL_REG (PLL_PERI0_CTRL_REG)
#define CCU_PLL_PERI1_CTRL_REG (PLL_PERI1_CTRL_REG)
#define CCU_PLL_GPU_CTRL_REG (PLL_GPU_CTRL_REG)
#define CCU_PLL_VIDE00_CTRL_REG (PLL_VIDEO0_CTRL_REG)
#define CCU_PLL_VIDE01_CTRL_REG (PLL_VIDEO1_CTRL_REG)
#define CCU_PLL_VIDE02_CTRL_REG (PLL_VIDEO2_CTRL_REG)
#define CCU_PLL_VIDE03_CTRL_REG (PLL_VIDEO3_CTRL_REG)
#define CCU_PLL_VE_CTRL_REG (PLL_VE_CTRL_REG)
#define CCU_PLL_CPUA_CLK_REG (SUNXI_CPU_SYS_CFG_BASE + 0x817000 + 0x60)
#define CCU_PLL_CPUB_CLK_REG (SUNXI_CPU_SYS_CFG_BASE + 0x817000 + 0x64)
#define CCU_PLL_CPU_CLK_REG (SUNXI_CPU_SYS_CFG_BASE + 0x817000 + 0x68)
#define CCU_PLL_DSU_CLK_REG (SUNXI_CPU_SYS_CFG_BASE + 0x817000 + 0x6C)
#define CCU_PLL_AUDIO_CTRL_REG (PLL_AUDIO_CTRL_REG)
#define CCU_PLL_HSIC_CTRL_REG (0x70)

/* cfg list */
#define CCU_CPUX_AXI_CFG_REG (CPU_CLK_REG)
#define CCU_AHB0_CFG_REG (0x510)
#define CCU_APB0_CFG_REG (0x520)
#define CCU_APB1_CFG_REG (0x524)
#define CCU_MBUS_CFG_REG (0x540)

#define CCU_CE_CLK_REG (0x680)
#define CCU_CE_BGR_REG (0x68C)

#define CCU_VE_CLK_REG (0x690)
#define CCU_VE_BGR_REG (0x69C)

/*SYS*/
#define CCU_DMA_BGR_REG (0x70C)
#define CCU_AVS_CLK_REG (0x750)
#define CCU_AVS_BGR_REG (0x74C)

/*IOMMU*/
#define CCU_IOMMU_BGR_REG (0x7bc)
#define IOMMU_AUTO_GATING_REG (SUNXI_IOMMU_BASE + 0X40)

/* storage */
#define CCU_DRAM_CLK_REG (0x800)
#define CCU_MBUS_MAT_CLK_GATING_REG (0x804)
#define CCU_PLL_DDR_AUX_REG (0x808)
#define CCU_DRAM_BGR_REG (0x80C)

#define CCU_NAND_CLK_REG (0x810)
#define CCU_NAND_BGR_REG (0x82C)

#define CCU_SMHC0_CLK_REG (0x830)
#define CCU_SMHC1_CLK_REG (0x834)
#define CCU_SMHC2_CLK_REG (0x838)
#define CCU_SMHC_BGR_REG (0x84c)

/*normal interface*/
#define CCU_UART_BGR_REG (0x90C)
#define CCU_TWI_BGR_REG (0x91C)
#define CCU_SCR_BGR_REG (0x93C)
#define CCU_SPI0_CLK_REG (0x940)
#define CCU_SPI1_CLK_REG (0x944)
#define CCU_SPI_BGR_REG (0x96C)
#define CCU_USB0_CLK_REG (0xA70)
#define CCU_USB_BGR_REG (0xA8C)

/*DMA*/
#define DMA_GATING_BASE CCU_DMA_BGR_REG
#define DMA_GATING_PASS (1)
#define DMA_GATING_BIT (0)

/*CE*/
#define CE_CLK_SRC_MASK (0x7)
#define CE_CLK_SRC_SEL_BIT (CE_CLK_REG_CLK_SRC_SEL_OFFSET)
#define CE_CLK_SRC (CE_CLK_REG_CLK_SRC_SEL_PERI0_400M)

#define CE_CLK_DIV_RATION_N_BIT (0)
#define CE_CLK_DIV_RATION_N_MASK (0x0)
#define CE_CLK_DIV_RATION_N (0)

#define CE_CLK_DIV_RATION_M_BIT (CE_CLK_REG_FACTOR_M_OFFSET)
#define CE_CLK_DIV_RATION_M_MASK (CE_CLK_REG_FACTOR_M_CLEAR_MASK)
#define CE_CLK_DIV_RATION_M (0)

#define CE_SCLK_ONOFF_BIT (31)
#define CE_SCLK_ON (1)

#define CE_GATING_BASE CCU_CE_BGR_REG
#define CE_GATING_PASS (1)
#define CE_GATING_BIT (0)

#define CE_RST_REG_BASE CCU_CE_BGR_REG

#define CE_SYS_RST_BIT (CE_BGR_REG_CE_SYS_RST_OFFSET)
#define CE_RST_BIT (CE_BGR_REG_CE_RST_OFFSET)
#define CE_DEASSERT (CE_BGR_REG_CE_SYS_RST_DE_ASSERT)
#define CE_SYS_GATING_BIT (CE_BGR_REG_CE_SYS_GATING_OFFSET)

/*gpadc gate and reset reg*/
#define CCU_GPADC_BGR_REG (0x09EC)
/*gpadc gate and reset reg*/
#define CCU_GPADC_CLK_REG (0x09E0)
/*lpadc gate and reset reg*/
#define CCU_LRADC_BGR_REG (0x0A9C)

/* ehci */
#define BUS_CLK_GATING_REG 0x60
#define BUS_SOFTWARE_RESET_REG 0x2c0
#define USBPHY_CONFIG_REG 0xcc

#define USBEHCI0_RST_BIT 24
#define USBEHCI0_GATIING_BIT 24
#define USBPHY0_RST_BIT 0
#define USBPHY0_SCLK_GATING_BIT 8

#define USBEHCI1_RST_BIT 25
#define USBEHCI1_GATIING_BIT 25
#define USBPHY1_RST_BIT 1
#define USBPHY1_SCLK_GATING_BIT 9

/* SPIF clock bit field */
#define CCM_SPIF_CTRL_M(x) ((x) -1)
#define CCM_SPIF_CTRL_N(x) ((x) << 8)
#define CCM_SPIF_CTRL_HOSC (0x0 << 24)
#define CCM_SPIF_CTRL_PERI400M (0x1 << 24)
#define CCM_SPIF_CTRL_PERI300M (0x2 << 24)
#define CCM_SPIF_CTRL_ENABLE (0x1 << 31)
#define GET_SPIF_CLK_SOURECS(x) (x == CCM_SPIF_CTRL_PERI400M ? 400000000 : 300000000)
#define CCM_SPIF_CTRL_PERI CCM_SPIF_CTRL_PERI400M
#define SPIF_RESET_SHIFT (19)
#define SPIF_GATING_SHIFT (3)

/*E906*/
#define RISCV_PUBSRAM_CFG_REG (SUNXI_DSP_PRCM_BASE + 0x0114)
#define RISCV_PUBSRAM_RST (0x1 << 16)
#define RISCV_PUBSRAM_GATING (0x1 << 0)

#define RISCV_CLK_REG (SUNXI_DSP_PRCM_BASE + 0x0120)
#define RISCV_CLK_GATING (0x1 << 31)

#define RISCV_CFG_BGR_REG (SUNXI_DSP_PRCM_BASE + 0x0124)
#define RISCV_CORE_RST (0x1 << 18)
#define RISCV_APB_DB_RST (0x1 << 17)
#define RISCV_CFG_RST (0x1 << 16)
#define RISCV_CFG_GATING (0x1 << 0)

#define RISCV_CFG_BASE (0x07130000)
#define RISCV_STA_ADD_REG (RISCV_CFG_BASE + 0x0204)

#endif// __SUN55IW3_REG_CCU_H__
